428 int mdfld_dsi_dpi_timing_calculation(struct drm_display_mode *mode,  in mdfld_dsi_dpi_timing_calculation()  argument
435 	pclk_hactive = mode->hdisplay;  in mdfld_dsi_dpi_timing_calculation()
436 	pclk_hfp = mode->hsync_start - mode->hdisplay;  in mdfld_dsi_dpi_timing_calculation()
437 	pclk_hsync = mode->hsync_end - mode->hsync_start;  in mdfld_dsi_dpi_timing_calculation()
438 	pclk_hbp = mode->htotal - mode->hsync_end;  in mdfld_dsi_dpi_timing_calculation()
440 	pclk_vfp = mode->vsync_start - mode->vdisplay;  in mdfld_dsi_dpi_timing_calculation()
441 	pclk_vsync = mode->vsync_end - mode->vsync_start;  in mdfld_dsi_dpi_timing_calculation()
442 	pclk_vbp = mode->vtotal - mode->vsync_end;  in mdfld_dsi_dpi_timing_calculation()
472 	struct drm_display_mode *mode = dsi_config->mode;  in mdfld_dsi_dpi_controller_init()  local
505 			(mode->vtotal * mode->htotal * dsi_config->bpp /  in mdfld_dsi_dpi_controller_init()
519 				mode->vdisplay << 16 | mode->hdisplay);  in mdfld_dsi_dpi_controller_init()
522 	mdfld_dsi_dpi_timing_calculation(mode, &dpi_timing,  in mdfld_dsi_dpi_controller_init()
681 void mdfld_dsi_dpi_dpms(struct drm_encoder *encoder, int mode)  in mdfld_dsi_dpi_dpms()  argument
683 	mdfld_dsi_dpi_set_power(encoder, mode == DRM_MODE_DPMS_ON);  in mdfld_dsi_dpi_dpms()
687 				     const struct drm_display_mode *mode,  in mdfld_dsi_dpi_mode_fixup()  argument
746 	struct drm_display_mode *mode = dsi_config->mode;  in mdfld_mipi_set_video_timing()  local
748 	mdfld_dsi_dpi_timing_calculation(mode, &dpi_timing,  in mdfld_mipi_set_video_timing()
753 		mode->vdisplay << 16 | mode->hdisplay);  in mdfld_mipi_set_video_timing()
795 	struct drm_display_mode *mode = dsi_config->mode;  in mdfld_set_pipe_timing()  local
797 	REG_WRITE(HTOTAL_A, ((mode->htotal - 1) << 16) | (mode->hdisplay - 1));  in mdfld_set_pipe_timing()
798 	REG_WRITE(HBLANK_A, ((mode->htotal - 1) << 16) | (mode->hdisplay - 1));  in mdfld_set_pipe_timing()
800 		((mode->hsync_end - 1) << 16) | (mode->hsync_start - 1));  in mdfld_set_pipe_timing()
802 	REG_WRITE(VTOTAL_A, ((mode->vtotal - 1) << 16) | (mode->vdisplay - 1));  in mdfld_set_pipe_timing()
803 	REG_WRITE(VBLANK_A, ((mode->vtotal - 1) << 16) | (mode->vdisplay - 1));  in mdfld_set_pipe_timing()
805 		((mode->vsync_end - 1) << 16) | (mode->vsync_start - 1));  in mdfld_set_pipe_timing()
808 		((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));  in mdfld_set_pipe_timing()
813 				   struct drm_display_mode *mode,  in mdfld_dsi_dpi_mode_set()  argument
873 			((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));  in mdfld_dsi_dpi_mode_set()