226 	int pipe = gma_crtc->pipe;  in cdv_dpll_set_clock_cdv()  local
229 	int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;  in cdv_dpll_set_clock_cdv()
230 	int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;  in cdv_dpll_set_clock_cdv()
243 	cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);  in cdv_dpll_set_clock_cdv()
266 	if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) {  in cdv_dpll_set_clock_cdv()
277 	ret = cdv_sb_read(dev, SB_M(pipe), &m);  in cdv_dpll_set_clock_cdv()
282 	ret = cdv_sb_write(dev, SB_M(pipe), m);  in cdv_dpll_set_clock_cdv()
286 	ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco);  in cdv_dpll_set_clock_cdv()
313 	ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco);  in cdv_dpll_set_clock_cdv()
317 	ret = cdv_sb_read(dev, SB_P(pipe), &p);  in cdv_dpll_set_clock_cdv()
339 	ret = cdv_sb_write(dev, SB_P(pipe), p);  in cdv_dpll_set_clock_cdv()
348 			lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);  in cdv_dpll_set_clock_cdv()
354 			lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);  in cdv_dpll_set_clock_cdv()
360 			lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);  in cdv_dpll_set_clock_cdv()
366 			lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);  in cdv_dpll_set_clock_cdv()
463 static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)  in cdv_intel_pipe_enabled()  argument
469 	crtc = dev_priv->pipe_to_crtc_mapping[pipe];  in cdv_intel_pipe_enabled()
526 		if (gma_crtc->pipe == 1 &&  in cdv_update_wm()
587 	int pipe = gma_crtc->pipe;  in cdv_intel_crtc_mode_set()  local
588 	const struct psb_offset *map = &dev_priv->regmap[pipe];  in cdv_intel_crtc_mode_set()
650 		if (pipe == 0)  in cdv_intel_crtc_mode_set()
684 		REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0);  in cdv_intel_crtc_mode_set()
685 		REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0);  in cdv_intel_crtc_mode_set()
686 		REG_WRITE(PIPE_DP_LINK_M(pipe), 0);  in cdv_intel_crtc_mode_set()
687 		REG_WRITE(PIPE_DP_LINK_N(pipe), 0);  in cdv_intel_crtc_mode_set()
728 	if (pipe == 0)  in cdv_intel_crtc_mode_set()
775 	if (cdv_intel_panel_fitter_pipe(dev) == pipe)  in cdv_intel_crtc_mode_set()
778 	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');  in cdv_intel_crtc_mode_set()
854 	int pipe = gma_crtc->pipe;  in cdv_intel_crtc_clock_get()  local
855 	const struct psb_offset *map = &dev_priv->regmap[pipe];  in cdv_intel_crtc_clock_get()
860 	struct psb_pipe *p = &dev_priv->regs.pipe[pipe];  in cdv_intel_crtc_clock_get()
868 		is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);  in cdv_intel_crtc_clock_get()
877 		is_lvds = (pipe == 1) &&  in cdv_intel_crtc_clock_get()
932 	int pipe = gma_crtc->pipe;  in cdv_intel_crtc_mode_get()  local
934 	struct psb_pipe *p = &dev_priv->regs.pipe[pipe];  in cdv_intel_crtc_mode_get()
935 	const struct psb_offset *map = &dev_priv->regmap[pipe];  in cdv_intel_crtc_mode_get()