Lines Matching refs:MXR_CFG
176 DUMPREG(MXR_CFG); in mixer_regs_dump()
292 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK); in mixer_cfg_scan()
333 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK); in mixer_cfg_rgb_fmt()
344 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE); in mixer_cfg_layer()
347 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE); in mixer_cfg_layer()
352 mixer_reg_writemask(res, MXR_CFG, val, in mixer_cfg_layer()
488 mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE); in mixer_layer_update()
649 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK); in mixer_win_reset()
652 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK); in mixer_win_reset()
699 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE); in mixer_win_reset()
700 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE); in mixer_win_reset()
702 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE); in mixer_win_reset()