127 static inline u32 vp_reg_read(struct mixer_resources *res, u32 reg_id)  in vp_reg_read()  argument
129 	return readl(res->vp_regs + reg_id);  in vp_reg_read()
132 static inline void vp_reg_write(struct mixer_resources *res, u32 reg_id,  in vp_reg_write()  argument
135 	writel(val, res->vp_regs + reg_id);  in vp_reg_write()
138 static inline void vp_reg_writemask(struct mixer_resources *res, u32 reg_id,  in vp_reg_writemask()  argument
141 	u32 old = vp_reg_read(res, reg_id);  in vp_reg_writemask()
144 	writel(val, res->vp_regs + reg_id);  in vp_reg_writemask()
147 static inline u32 mixer_reg_read(struct mixer_resources *res, u32 reg_id)  in mixer_reg_read()  argument
149 	return readl(res->mixer_regs + reg_id);  in mixer_reg_read()
152 static inline void mixer_reg_write(struct mixer_resources *res, u32 reg_id,  in mixer_reg_write()  argument
155 	writel(val, res->mixer_regs + reg_id);  in mixer_reg_write()
158 static inline void mixer_reg_writemask(struct mixer_resources *res,  in mixer_reg_writemask()  argument
161 	u32 old = mixer_reg_read(res, reg_id);  in mixer_reg_writemask()
164 	writel(val, res->mixer_regs + reg_id);  in mixer_reg_writemask()
234 static inline void vp_filter_set(struct mixer_resources *res,  in vp_filter_set()  argument
242 		vp_reg_write(res, reg_id, val);  in vp_filter_set()
246 static void vp_default_filter(struct mixer_resources *res)  in vp_default_filter()  argument
248 	vp_filter_set(res, VP_POLY8_Y0_LL,  in vp_default_filter()
250 	vp_filter_set(res, VP_POLY4_Y0_LL,  in vp_default_filter()
252 	vp_filter_set(res, VP_POLY4_C0_LL,  in vp_default_filter()
258 	struct mixer_resources *res = &ctx->mixer_res;  in mixer_vsync_set_update()  local
261 	mixer_reg_writemask(res, MXR_STATUS, enable ?  in mixer_vsync_set_update()
265 		vp_reg_write(res, VP_SHADOW_UPDATE, enable ?  in mixer_vsync_set_update()
271 	struct mixer_resources *res = &ctx->mixer_res;  in mixer_cfg_scan()  local
292 	mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK);  in mixer_cfg_scan()
297 	struct mixer_resources *res = &ctx->mixer_res;  in mixer_cfg_rgb_fmt()  local
306 		mixer_reg_write(res, MXR_CM_COEFF_Y,  in mixer_cfg_rgb_fmt()
309 		mixer_reg_write(res, MXR_CM_COEFF_CB,  in mixer_cfg_rgb_fmt()
311 		mixer_reg_write(res, MXR_CM_COEFF_CR,  in mixer_cfg_rgb_fmt()
315 		mixer_reg_write(res, MXR_CM_COEFF_Y,  in mixer_cfg_rgb_fmt()
318 		mixer_reg_write(res, MXR_CM_COEFF_CB,  in mixer_cfg_rgb_fmt()
320 		mixer_reg_write(res, MXR_CM_COEFF_CR,  in mixer_cfg_rgb_fmt()
324 		mixer_reg_write(res, MXR_CM_COEFF_Y,  in mixer_cfg_rgb_fmt()
327 		mixer_reg_write(res, MXR_CM_COEFF_CB,  in mixer_cfg_rgb_fmt()
329 		mixer_reg_write(res, MXR_CM_COEFF_CR,  in mixer_cfg_rgb_fmt()
333 	mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);  in mixer_cfg_rgb_fmt()
339 	struct mixer_resources *res = &ctx->mixer_res;  in mixer_cfg_layer()  local
344 		mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);  in mixer_cfg_layer()
347 		mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);  in mixer_cfg_layer()
351 			vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON);  in mixer_cfg_layer()
352 			mixer_reg_writemask(res, MXR_CFG, val,  in mixer_cfg_layer()
356 			mixer_reg_writemask(res, MXR_GRAPHIC_CFG(0), val,  in mixer_cfg_layer()
366 	struct mixer_resources *res = &ctx->mixer_res;  in mixer_run()  local
368 	mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);  in mixer_run()
373 	struct mixer_resources *res = &ctx->mixer_res;  in mixer_stop()  local
376 	mixer_reg_writemask(res, MXR_STATUS, 0, MXR_STATUS_REG_RUN);  in mixer_stop()
378 	while (!(mixer_reg_read(res, MXR_STATUS) & MXR_STATUS_REG_IDLE) &&  in mixer_stop()
385 	struct mixer_resources *res = &ctx->mixer_res;  in vp_video_buffer()  local
426 	spin_lock_irqsave(&res->reg_slock, flags);  in vp_video_buffer()
431 	vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP);  in vp_video_buffer()
436 	vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK);  in vp_video_buffer()
439 	vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(plane->pitch) |  in vp_video_buffer()
442 	vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(plane->pitch) |  in vp_video_buffer()
445 	vp_reg_write(res, VP_SRC_WIDTH, plane->src_width);  in vp_video_buffer()
446 	vp_reg_write(res, VP_SRC_HEIGHT, plane->src_height);  in vp_video_buffer()
447 	vp_reg_write(res, VP_SRC_H_POSITION,  in vp_video_buffer()
449 	vp_reg_write(res, VP_SRC_V_POSITION, plane->src_y);  in vp_video_buffer()
451 	vp_reg_write(res, VP_DST_WIDTH, plane->crtc_width);  in vp_video_buffer()
452 	vp_reg_write(res, VP_DST_H_POSITION, plane->crtc_x);  in vp_video_buffer()
454 		vp_reg_write(res, VP_DST_HEIGHT, plane->crtc_height / 2);  in vp_video_buffer()
455 		vp_reg_write(res, VP_DST_V_POSITION, plane->crtc_y / 2);  in vp_video_buffer()
457 		vp_reg_write(res, VP_DST_HEIGHT, plane->crtc_height);  in vp_video_buffer()
458 		vp_reg_write(res, VP_DST_V_POSITION, plane->crtc_y);  in vp_video_buffer()
461 	vp_reg_write(res, VP_H_RATIO, plane->h_ratio);  in vp_video_buffer()
462 	vp_reg_write(res, VP_V_RATIO, plane->v_ratio);  in vp_video_buffer()
464 	vp_reg_write(res, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE);  in vp_video_buffer()
467 	vp_reg_write(res, VP_TOP_Y_PTR, luma_addr[0]);  in vp_video_buffer()
468 	vp_reg_write(res, VP_BOT_Y_PTR, luma_addr[1]);  in vp_video_buffer()
469 	vp_reg_write(res, VP_TOP_C_PTR, chroma_addr[0]);  in vp_video_buffer()
470 	vp_reg_write(res, VP_BOT_C_PTR, chroma_addr[1]);  in vp_video_buffer()
478 	spin_unlock_irqrestore(&res->reg_slock, flags);  in vp_video_buffer()
486 	struct mixer_resources *res = &ctx->mixer_res;  in mixer_layer_update()  local
488 	mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);  in mixer_layer_update()
517 	struct mixer_resources *res = &ctx->mixer_res;  in mixer_graph_buffer()  local
570 	spin_lock_irqsave(&res->reg_slock, flags);  in mixer_graph_buffer()
574 	mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win),  in mixer_graph_buffer()
578 	mixer_reg_write(res, MXR_GRAPHIC_SPAN(win),  in mixer_graph_buffer()
586 		mixer_reg_write(res, MXR_RESOLUTION, val);  in mixer_graph_buffer()
593 	mixer_reg_write(res, MXR_GRAPHIC_WH(win), val);  in mixer_graph_buffer()
598 	mixer_reg_write(res, MXR_GRAPHIC_SXY(win), val);  in mixer_graph_buffer()
603 	mixer_reg_write(res, MXR_GRAPHIC_DXY(win), val);  in mixer_graph_buffer()
606 	mixer_reg_write(res, MXR_GRAPHIC_BASE(win), dma_addr);  in mixer_graph_buffer()
620 	spin_unlock_irqrestore(&res->reg_slock, flags);  in mixer_graph_buffer()
627 	struct mixer_resources *res = &ctx->mixer_res;  in vp_win_reset()  local
630 	vp_reg_write(res, VP_SRESET, VP_SRESET_PROCESSING);  in vp_win_reset()
633 		if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING)  in vp_win_reset()
642 	struct mixer_resources *res = &ctx->mixer_res;  in mixer_win_reset()  local
646 	spin_lock_irqsave(&res->reg_slock, flags);  in mixer_win_reset()
649 	mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK);  in mixer_win_reset()
652 	mixer_reg_writemask(res, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK);  in mixer_win_reset()
655 	mixer_reg_writemask(res, MXR_STATUS, MXR_STATUS_16_BURST,  in mixer_win_reset()
668 	mixer_reg_write(res, MXR_LAYER_CFG, val);  in mixer_win_reset()
671 	mixer_reg_write(res, MXR_BG_COLOR0, 0x008080);  in mixer_win_reset()
672 	mixer_reg_write(res, MXR_BG_COLOR1, 0x008080);  in mixer_win_reset()
673 	mixer_reg_write(res, MXR_BG_COLOR2, 0x008080);  in mixer_win_reset()
681 	mixer_reg_write(res, MXR_GRAPHIC_CFG(0), val);  in mixer_win_reset()
686 	mixer_reg_write(res, MXR_GRAPHIC_CFG(1), val);  in mixer_win_reset()
690 	mixer_reg_write(res, MXR_VIDEO_CFG, val);  in mixer_win_reset()
695 		vp_default_filter(res);  in mixer_win_reset()
699 	mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);  in mixer_win_reset()
700 	mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);  in mixer_win_reset()
702 		mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);  in mixer_win_reset()
705 	spin_unlock_irqrestore(&res->reg_slock, flags);  in mixer_win_reset()
711 	struct mixer_resources *res = &ctx->mixer_res;  in mixer_irq_handler()  local
714 	spin_lock(&res->reg_slock);  in mixer_irq_handler()
717 	val = mixer_reg_read(res, MXR_INT_STATUS);  in mixer_irq_handler()
723 			base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));  in mixer_irq_handler()
724 			shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0));  in mixer_irq_handler()
728 			base = mixer_reg_read(res, MXR_GRAPHIC_BASE(1));  in mixer_irq_handler()
729 			shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(1));  in mixer_irq_handler()
751 	mixer_reg_write(res, MXR_INT_STATUS, val);  in mixer_irq_handler()
753 	spin_unlock(&res->reg_slock);  in mixer_irq_handler()
762 	struct resource *res;  in mixer_resources_init()  local
784 	res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 0);  in mixer_resources_init()
785 	if (res == NULL) {  in mixer_resources_init()
790 	mixer_res->mixer_regs = devm_ioremap(dev, res->start,  in mixer_resources_init()
791 							resource_size(res));  in mixer_resources_init()
797 	res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_IRQ, 0);  in mixer_resources_init()
798 	if (res == NULL) {  in mixer_resources_init()
803 	ret = devm_request_irq(dev, res->start, mixer_irq_handler,  in mixer_resources_init()
809 	mixer_res->irq = res->start;  in mixer_resources_init()
818 	struct resource *res;  in vp_resources_init()  local
843 	res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 1);  in vp_resources_init()
844 	if (res == NULL) {  in vp_resources_init()
849 	mixer_res->vp_regs = devm_ioremap(dev, res->start,  in vp_resources_init()
850 							resource_size(res));  in vp_resources_init()
900 	struct mixer_resources *res = &mixer_ctx->mixer_res;  in mixer_enable_vblank()  local
908 	mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,  in mixer_enable_vblank()
917 	struct mixer_resources *res = &mixer_ctx->mixer_res;  in mixer_disable_vblank()  local
920 	mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC);  in mixer_disable_vblank()
947 	struct mixer_resources *res = &mixer_ctx->mixer_res;  in mixer_win_disable()  local
960 	spin_lock_irqsave(&res->reg_slock, flags);  in mixer_win_disable()
966 	spin_unlock_irqrestore(&res->reg_slock, flags);  in mixer_win_disable()
1032 	struct mixer_resources *res = &ctx->mixer_res;  in mixer_poweron()  local
1044 	clk_prepare_enable(res->mixer);  in mixer_poweron()
1045 	clk_prepare_enable(res->hdmi);  in mixer_poweron()
1047 		clk_prepare_enable(res->vp);  in mixer_poweron()
1049 			clk_prepare_enable(res->sclk_mixer);  in mixer_poweron()
1056 	mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);  in mixer_poweron()
1058 	mixer_reg_write(res, MXR_INT_EN, ctx->int_en);  in mixer_poweron()
1066 	struct mixer_resources *res = &ctx->mixer_res;  in mixer_poweroff()  local
1079 	ctx->int_en = mixer_reg_read(res, MXR_INT_EN);  in mixer_poweroff()
1085 	clk_disable_unprepare(res->hdmi);  in mixer_poweroff()
1086 	clk_disable_unprepare(res->mixer);  in mixer_poweroff()
1088 		clk_disable_unprepare(res->vp);  in mixer_poweroff()
1090 			clk_disable_unprepare(res->sclk_mixer);  in mixer_poweroff()