92 	unsigned int timing_base;  member
105 	.timing_base = 0x0,
111 	.timing_base = 0x20000,
119 	.timing_base = 0x0,
128 	.timing_base = 0x20000,
138 	.timing_base = 0x20000,
342 	void *timing_base = ctx->regs + driver_data->timing_base;  in fimd_commit()  local
354 		writel(val, timing_base + I80IFCONFAx(0));  in fimd_commit()
357 		writel(0, timing_base + I80IFCONFBx(0));  in fimd_commit()
378 		writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);  in fimd_commit()
388 		writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);  in fimd_commit()
398 		writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);  in fimd_commit()
402 		writel(ctx->vidout_con, timing_base + VIDOUT_CON);  in fimd_commit()
418 	writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);  in fimd_commit()
899 	void *timing_base = ctx->regs + driver_data->timing_base;  in fimd_trigger()  local
912 	reg = readl(timing_base + TRIGCON);  in fimd_trigger()
914 	writel(reg, timing_base + TRIGCON);  in fimd_trigger()