114 	dev->node_props.cpu_cores_count = cu->num_cpu_cores;  in kfd_populated_cu_info_cpu()
115 	dev->node_props.cpu_core_id_base = cu->processor_id_low;  in kfd_populated_cu_info_cpu()
117 		dev->node_props.capability |= HSA_CAP_ATS_PRESENT;  in kfd_populated_cu_info_cpu()
129 	dev->node_props.simd_id_base = cu->processor_id_low;  in kfd_populated_cu_info_gpu()
130 	dev->node_props.simd_count = cu->num_simd_cores;  in kfd_populated_cu_info_gpu()
131 	dev->node_props.lds_size_in_kb = cu->lds_size_in_kb;  in kfd_populated_cu_info_gpu()
132 	dev->node_props.max_waves_per_simd = cu->max_waves_simd;  in kfd_populated_cu_info_gpu()
133 	dev->node_props.wave_front_size = cu->wave_front_size;  in kfd_populated_cu_info_gpu()
134 	dev->node_props.mem_banks_count = cu->num_banks;  in kfd_populated_cu_info_gpu()
135 	dev->node_props.array_count = cu->num_arrays;  in kfd_populated_cu_info_gpu()
136 	dev->node_props.cu_per_simd_array = cu->num_cu_per_array;  in kfd_populated_cu_info_gpu()
137 	dev->node_props.simd_per_cu = cu->num_simd_per_cu;  in kfd_populated_cu_info_gpu()
138 	dev->node_props.max_slots_scratch_cu = cu->max_slots_scatch_cu;  in kfd_populated_cu_info_gpu()
140 		dev->node_props.capability |= HSA_CAP_HOT_PLUGGABLE;  in kfd_populated_cu_info_gpu()
190 			if (dev->node_props.cpu_cores_count == 0)  in kfd_parse_subtype_mem()
232 		if (id == dev->node_props.cpu_core_id_base ||  in kfd_parse_subtype_cache()
233 		    id == dev->node_props.simd_id_base) {  in kfd_parse_subtype_cache()
256 			dev->node_props.caches_count++;  in kfd_parse_subtype_cache()
307 			dev->node_props.io_links_count++;  in kfd_parse_subtype_iolink()
653 					(char)dev->node_props.marketing_name[i];  in node_show()
654 			if (dev->node_props.marketing_name[i] == 0)  in node_show()
664 			dev->node_props.cpu_cores_count);  in node_show()
666 			dev->node_props.simd_count);  in node_show()
668 	if (dev->mem_bank_count < dev->node_props.mem_banks_count) {  in node_show()
670 				dev->node_props.mem_banks_count,  in node_show()
676 				dev->node_props.mem_banks_count);  in node_show()
680 			dev->node_props.caches_count);  in node_show()
682 			dev->node_props.io_links_count);  in node_show()
684 			dev->node_props.cpu_core_id_base);  in node_show()
686 			dev->node_props.simd_id_base);  in node_show()
688 			dev->node_props.max_waves_per_simd);  in node_show()
690 			dev->node_props.lds_size_in_kb);  in node_show()
692 			dev->node_props.gds_size_in_kb);  in node_show()
694 			dev->node_props.wave_front_size);  in node_show()
696 			dev->node_props.array_count);  in node_show()
698 			dev->node_props.simd_arrays_per_engine);  in node_show()
700 			dev->node_props.cu_per_simd_array);  in node_show()
702 			dev->node_props.simd_per_cu);  in node_show()
704 			dev->node_props.max_slots_scratch_cu);  in node_show()
706 			dev->node_props.vendor_id);  in node_show()
708 			dev->node_props.device_id);  in node_show()
710 			dev->node_props.location_id);  in node_show()
717 			dev->node_props.capability |=  in node_show()
720 			dev->node_props.capability |=  in node_show()
738 				dev->node_props.capability);  in node_show()
1083 		pr_info("\tCPU count: %d\n", dev->node_props.cpu_cores_count);  in kfd_debug_print_topology()
1084 		pr_info("\tSIMD count: %d", dev->node_props.simd_count);  in kfd_debug_print_topology()
1121 		if (dev->gpu == NULL && dev->node_props.simd_count > 0) {  in kfd_assign_gpu()
1181 	dev->node_props.vendor_id = gpu->pdev->vendor;  in kfd_topology_add_device()
1182 	dev->node_props.device_id = gpu->pdev->device;  in kfd_topology_add_device()
1183 	dev->node_props.location_id = (gpu->pdev->bus->number << 24) +  in kfd_topology_add_device()