95 	void __iomem *base_addr;  member
166 	data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
206 	writel_relaxed(state, gpio->base_addr + reg_offset);  in zynq_gpio_set_value()
232 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_in()
234 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_in()
261 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_out()
263 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_out()
266 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));  in zynq_gpio_dir_out()
268 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));  in zynq_gpio_dir_out()
291 		       gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));  in zynq_gpio_irq_mask()
311 		       gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));  in zynq_gpio_irq_unmask()
330 		       gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));  in zynq_gpio_irq_ack()
380 	int_type = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
382 	int_pol = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
384 	int_any = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
419 		       gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
421 		       gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
423 		       gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
509 		int_sts = readl_relaxed(gpio->base_addr +  in zynq_gpio_irqhandler()
511 		int_enb = readl_relaxed(gpio->base_addr +  in zynq_gpio_irqhandler()
610 	gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);  in zynq_gpio_probe()
611 	if (IS_ERR(gpio->base_addr))  in zynq_gpio_probe()
612 		return PTR_ERR(gpio->base_addr);  in zynq_gpio_probe()
655 		writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +  in zynq_gpio_probe()