Lines Matching refs:bank_num
114 unsigned int *bank_num, in zynq_gpio_get_bank_pin() argument
119 *bank_num = 0; in zynq_gpio_get_bank_pin()
123 *bank_num = 1; in zynq_gpio_get_bank_pin()
127 *bank_num = 2; in zynq_gpio_get_bank_pin()
131 *bank_num = 3; in zynq_gpio_get_bank_pin()
136 *bank_num = 0; in zynq_gpio_get_bank_pin()
161 unsigned int bank_num, bank_pin_num; in zynq_gpio_get_value() local
164 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num); in zynq_gpio_get_value()
167 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); in zynq_gpio_get_value()
185 unsigned int reg_offset, bank_num, bank_pin_num; in zynq_gpio_set_value() local
188 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num); in zynq_gpio_set_value()
193 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); in zynq_gpio_set_value()
195 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); in zynq_gpio_set_value()
222 unsigned int bank_num, bank_pin_num; in zynq_gpio_dir_in() local
225 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num); in zynq_gpio_dir_in()
228 if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8)) in zynq_gpio_dir_in()
232 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
234 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
255 unsigned int bank_num, bank_pin_num; in zynq_gpio_dir_out() local
258 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num); in zynq_gpio_dir_out()
261 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()
263 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()
266 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_dir_out()
268 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_dir_out()
285 unsigned int device_pin_num, bank_num, bank_pin_num; in zynq_gpio_irq_mask() local
289 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num); in zynq_gpio_irq_mask()
291 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); in zynq_gpio_irq_mask()
305 unsigned int device_pin_num, bank_num, bank_pin_num; in zynq_gpio_irq_unmask() local
309 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num); in zynq_gpio_irq_unmask()
311 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num)); in zynq_gpio_irq_unmask()
324 unsigned int device_pin_num, bank_num, bank_pin_num; in zynq_gpio_irq_ack() local
328 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num); in zynq_gpio_irq_ack()
330 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); in zynq_gpio_irq_ack()
374 unsigned int device_pin_num, bank_num, bank_pin_num; in zynq_gpio_set_irq_type() local
378 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num); in zynq_gpio_set_irq_type()
381 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
383 ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
385 ZYNQ_GPIO_INTANY_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
419 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
421 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
423 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
470 unsigned int bank_num, in zynq_gpio_handle_bank_irq() argument
473 unsigned int bank_offset = zynq_gpio_bank_offset[bank_num]; in zynq_gpio_handle_bank_irq()
502 unsigned int bank_num; in zynq_gpio_irqhandler() local
508 for (bank_num = 0; bank_num < ZYNQ_GPIO_MAX_BANK; bank_num++) { in zynq_gpio_irqhandler()
510 ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); in zynq_gpio_irqhandler()
512 ZYNQ_GPIO_INTMASK_OFFSET(bank_num)); in zynq_gpio_irqhandler()
513 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb); in zynq_gpio_irqhandler()
598 int ret, bank_num; in zynq_gpio_probe() local
654 for (bank_num = 0; bank_num < ZYNQ_GPIO_MAX_BANK; bank_num++) in zynq_gpio_probe()
656 ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); in zynq_gpio_probe()