60 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)  in gpio_rcar_read()  argument
62 	return ioread32(p->base + offs);  in gpio_rcar_read()
65 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,  in gpio_rcar_write()  argument
68 	iowrite32(value, p->base + offs);  in gpio_rcar_write()
71 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,  in gpio_rcar_modify_bit()  argument
74 	u32 tmp = gpio_rcar_read(p, offs);  in gpio_rcar_modify_bit()
81 	gpio_rcar_write(p, offs, tmp);  in gpio_rcar_modify_bit()
87 	struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,  in gpio_rcar_irq_disable()  local
90 	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));  in gpio_rcar_irq_disable()
96 	struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,  in gpio_rcar_irq_enable()  local
99 	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));  in gpio_rcar_irq_enable()
102 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,  in gpio_rcar_config_interrupt_input_mode()  argument
115 	spin_lock_irqsave(&p->lock, flags);  in gpio_rcar_config_interrupt_input_mode()
118 	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);  in gpio_rcar_config_interrupt_input_mode()
121 	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);  in gpio_rcar_config_interrupt_input_mode()
124 	if (p->config.has_both_edge_trigger)  in gpio_rcar_config_interrupt_input_mode()
125 		gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);  in gpio_rcar_config_interrupt_input_mode()
128 	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);  in gpio_rcar_config_interrupt_input_mode()
132 		gpio_rcar_write(p, INTCLR, BIT(hwirq));  in gpio_rcar_config_interrupt_input_mode()
134 	spin_unlock_irqrestore(&p->lock, flags);  in gpio_rcar_config_interrupt_input_mode()
140 	struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,  in gpio_rcar_irq_set_type()  local
144 	dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);  in gpio_rcar_irq_set_type()
148 		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,  in gpio_rcar_irq_set_type()
152 		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,  in gpio_rcar_irq_set_type()
156 		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,  in gpio_rcar_irq_set_type()
160 		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,  in gpio_rcar_irq_set_type()
164 		if (!p->config.has_both_edge_trigger)  in gpio_rcar_irq_set_type()
166 		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,  in gpio_rcar_irq_set_type()
178 	struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,  in gpio_rcar_irq_set_wake()  local
182 	if (p->irq_parent) {  in gpio_rcar_irq_set_wake()
183 		error = irq_set_irq_wake(p->irq_parent, on);  in gpio_rcar_irq_set_wake()
185 			dev_dbg(&p->pdev->dev,  in gpio_rcar_irq_set_wake()
187 				p->irq_parent);  in gpio_rcar_irq_set_wake()
188 			p->irq_parent = 0;  in gpio_rcar_irq_set_wake()
192 	if (!p->clk)  in gpio_rcar_irq_set_wake()
196 		clk_enable(p->clk);  in gpio_rcar_irq_set_wake()
198 		clk_disable(p->clk);  in gpio_rcar_irq_set_wake()
205 	struct gpio_rcar_priv *p = dev_id;  in gpio_rcar_irq_handler()  local
209 	while ((pending = gpio_rcar_read(p, INTDT) &  in gpio_rcar_irq_handler()
210 			  gpio_rcar_read(p, INTMSK))) {  in gpio_rcar_irq_handler()
212 		gpio_rcar_write(p, INTCLR, BIT(offset));  in gpio_rcar_irq_handler()
213 		generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain,  in gpio_rcar_irq_handler()
230 	struct gpio_rcar_priv *p = gpio_to_priv(chip);  in gpio_rcar_config_general_input_output_mode()  local
238 	spin_lock_irqsave(&p->lock, flags);  in gpio_rcar_config_general_input_output_mode()
241 	gpio_rcar_modify_bit(p, POSNEG, gpio, false);  in gpio_rcar_config_general_input_output_mode()
244 	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);  in gpio_rcar_config_general_input_output_mode()
247 	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);  in gpio_rcar_config_general_input_output_mode()
249 	spin_unlock_irqrestore(&p->lock, flags);  in gpio_rcar_config_general_input_output_mode()
287 	struct gpio_rcar_priv *p = gpio_to_priv(chip);  in gpio_rcar_set()  local
290 	spin_lock_irqsave(&p->lock, flags);  in gpio_rcar_set()
291 	gpio_rcar_modify_bit(p, OUTDT, offset, value);  in gpio_rcar_set()
292 	spin_unlock_irqrestore(&p->lock, flags);  in gpio_rcar_set()
339 static int gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)  in gpio_rcar_parse_pdata()  argument
341 	struct gpio_rcar_config *pdata = dev_get_platdata(&p->pdev->dev);  in gpio_rcar_parse_pdata()
342 	struct device_node *np = p->pdev->dev.of_node;  in gpio_rcar_parse_pdata()
347 		p->config = *pdata;  in gpio_rcar_parse_pdata()
360 		p->config.number_of_pins = ret == 0 ? args.args[2]  in gpio_rcar_parse_pdata()
362 		p->config.gpio_base = -1;  in gpio_rcar_parse_pdata()
363 		p->config.has_both_edge_trigger = info->has_both_edge_trigger;  in gpio_rcar_parse_pdata()
366 	if (p->config.number_of_pins == 0 ||  in gpio_rcar_parse_pdata()
367 	    p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) {  in gpio_rcar_parse_pdata()
368 		dev_warn(&p->pdev->dev,  in gpio_rcar_parse_pdata()
370 			 p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK);  in gpio_rcar_parse_pdata()
371 		p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK;  in gpio_rcar_parse_pdata()
379 	struct gpio_rcar_priv *p;  in gpio_rcar_probe()  local
387 	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);  in gpio_rcar_probe()
388 	if (!p)  in gpio_rcar_probe()
391 	p->pdev = pdev;  in gpio_rcar_probe()
392 	spin_lock_init(&p->lock);  in gpio_rcar_probe()
395 	ret = gpio_rcar_parse_pdata(p);  in gpio_rcar_probe()
399 	platform_set_drvdata(pdev, p);  in gpio_rcar_probe()
401 	p->clk = devm_clk_get(dev, NULL);  in gpio_rcar_probe()
402 	if (IS_ERR(p->clk)) {  in gpio_rcar_probe()
404 		p->clk = NULL;  in gpio_rcar_probe()
419 	p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));  in gpio_rcar_probe()
420 	if (!p->base) {  in gpio_rcar_probe()
426 	gpio_chip = &p->gpio_chip;  in gpio_rcar_probe()
436 	gpio_chip->base = p->config.gpio_base;  in gpio_rcar_probe()
437 	gpio_chip->ngpio = p->config.number_of_pins;  in gpio_rcar_probe()
439 	irq_chip = &p->irq_chip;  in gpio_rcar_probe()
453 	ret = gpiochip_irqchip_add(gpio_chip, irq_chip, p->config.irq_base,  in gpio_rcar_probe()
460 	p->irq_parent = irq->start;  in gpio_rcar_probe()
462 			     IRQF_SHARED, name, p)) {  in gpio_rcar_probe()
468 	dev_info(dev, "driving %d GPIOs\n", p->config.number_of_pins);  in gpio_rcar_probe()
471 	if (p->config.irq_base) {  in gpio_rcar_probe()
473 		if (p->config.irq_base != ret)  in gpio_rcar_probe()
475 				 p->config.irq_base, ret);  in gpio_rcar_probe()
478 	if (p->config.pctl_name) {  in gpio_rcar_probe()
479 		ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,  in gpio_rcar_probe()
497 	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);  in gpio_rcar_remove()  local
499 	gpiochip_remove(&p->gpio_chip);  in gpio_rcar_remove()