Lines Matching refs:chip
68 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_gpio_request() local
71 if (chip->uses_pinctrl) in pl061_gpio_request()
78 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_gpio_free() local
81 if (chip->uses_pinctrl) in pl061_gpio_free()
87 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_direction_input() local
94 spin_lock_irqsave(&chip->lock, flags); in pl061_direction_input()
95 gpiodir = readb(chip->base + GPIODIR); in pl061_direction_input()
97 writeb(gpiodir, chip->base + GPIODIR); in pl061_direction_input()
98 spin_unlock_irqrestore(&chip->lock, flags); in pl061_direction_input()
106 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_direction_output() local
113 spin_lock_irqsave(&chip->lock, flags); in pl061_direction_output()
114 writeb(!!value << offset, chip->base + (BIT(offset + 2))); in pl061_direction_output()
115 gpiodir = readb(chip->base + GPIODIR); in pl061_direction_output()
117 writeb(gpiodir, chip->base + GPIODIR); in pl061_direction_output()
123 writeb(!!value << offset, chip->base + (BIT(offset + 2))); in pl061_direction_output()
124 spin_unlock_irqrestore(&chip->lock, flags); in pl061_direction_output()
131 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_get_value() local
133 return !!readb(chip->base + (BIT(offset + 2))); in pl061_get_value()
138 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_set_value() local
140 writeb(!!value << offset, chip->base + (BIT(offset + 2))); in pl061_set_value()
146 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_irq_type() local
155 spin_lock_irqsave(&chip->lock, flags); in pl061_irq_type()
157 gpioiev = readb(chip->base + GPIOIEV); in pl061_irq_type()
158 gpiois = readb(chip->base + GPIOIS); in pl061_irq_type()
159 gpioibe = readb(chip->base + GPIOIBE); in pl061_irq_type()
181 writeb(gpiois, chip->base + GPIOIS); in pl061_irq_type()
182 writeb(gpioibe, chip->base + GPIOIBE); in pl061_irq_type()
183 writeb(gpioiev, chip->base + GPIOIEV); in pl061_irq_type()
185 spin_unlock_irqrestore(&chip->lock, flags); in pl061_irq_type()
195 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_irq_handler() local
200 pending = readb(chip->base + GPIOMIS); in pl061_irq_handler()
201 writeb(pending, chip->base + GPIOIC); in pl061_irq_handler()
214 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_irq_mask() local
218 spin_lock(&chip->lock); in pl061_irq_mask()
219 gpioie = readb(chip->base + GPIOIE) & ~mask; in pl061_irq_mask()
220 writeb(gpioie, chip->base + GPIOIE); in pl061_irq_mask()
221 spin_unlock(&chip->lock); in pl061_irq_mask()
227 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); in pl061_irq_unmask() local
231 spin_lock(&chip->lock); in pl061_irq_unmask()
232 gpioie = readb(chip->base + GPIOIE) | mask; in pl061_irq_unmask()
233 writeb(gpioie, chip->base + GPIOIE); in pl061_irq_unmask()
234 spin_unlock(&chip->lock); in pl061_irq_unmask()
248 struct pl061_gpio *chip; in pl061_probe() local
251 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); in pl061_probe()
252 if (chip == NULL) in pl061_probe()
256 chip->gc.base = pdata->gpio_base; in pl061_probe()
263 chip->gc.base = -1; in pl061_probe()
267 chip->base = devm_ioremap_resource(dev, &adev->res); in pl061_probe()
268 if (IS_ERR(chip->base)) in pl061_probe()
269 return PTR_ERR(chip->base); in pl061_probe()
271 spin_lock_init(&chip->lock); in pl061_probe()
273 chip->uses_pinctrl = true; in pl061_probe()
275 chip->gc.request = pl061_gpio_request; in pl061_probe()
276 chip->gc.free = pl061_gpio_free; in pl061_probe()
277 chip->gc.direction_input = pl061_direction_input; in pl061_probe()
278 chip->gc.direction_output = pl061_direction_output; in pl061_probe()
279 chip->gc.get = pl061_get_value; in pl061_probe()
280 chip->gc.set = pl061_set_value; in pl061_probe()
281 chip->gc.ngpio = PL061_GPIO_NR; in pl061_probe()
282 chip->gc.label = dev_name(dev); in pl061_probe()
283 chip->gc.dev = dev; in pl061_probe()
284 chip->gc.owner = THIS_MODULE; in pl061_probe()
286 ret = gpiochip_add(&chip->gc); in pl061_probe()
293 writeb(0, chip->base + GPIOIE); /* disable irqs */ in pl061_probe()
300 ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip, in pl061_probe()
307 gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip, in pl061_probe()
313 pl061_direction_output(&chip->gc, i, in pl061_probe()
316 pl061_direction_input(&chip->gc, i); in pl061_probe()
320 amba_set_drvdata(adev, chip); in pl061_probe()
330 struct pl061_gpio *chip = dev_get_drvdata(dev); in pl061_suspend() local
333 chip->csave_regs.gpio_data = 0; in pl061_suspend()
334 chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR); in pl061_suspend()
335 chip->csave_regs.gpio_is = readb(chip->base + GPIOIS); in pl061_suspend()
336 chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE); in pl061_suspend()
337 chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV); in pl061_suspend()
338 chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE); in pl061_suspend()
341 if (chip->csave_regs.gpio_dir & (BIT(offset))) in pl061_suspend()
342 chip->csave_regs.gpio_data |= in pl061_suspend()
343 pl061_get_value(&chip->gc, offset) << offset; in pl061_suspend()
351 struct pl061_gpio *chip = dev_get_drvdata(dev); in pl061_resume() local
355 if (chip->csave_regs.gpio_dir & (BIT(offset))) in pl061_resume()
356 pl061_direction_output(&chip->gc, offset, in pl061_resume()
357 chip->csave_regs.gpio_data & in pl061_resume()
360 pl061_direction_input(&chip->gc, offset); in pl061_resume()
363 writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS); in pl061_resume()
364 writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE); in pl061_resume()
365 writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV); in pl061_resume()
366 writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE); in pl061_resume()