11 static void (*nb_bus_decoder)(int node_id, struct mce *m);
292 static void decode_mc0_mce(struct mce *m)  in decode_mc0_mce()  argument
294 	u16 ec = EC(m->status);  in decode_mc0_mce()
295 	u8 xec = XEC(m->status, xec_mask);  in decode_mc0_mce()
402 static void decode_mc1_mce(struct mce *m)  in decode_mc1_mce()  argument
404 	u16 ec = EC(m->status);  in decode_mc1_mce()
405 	u8 xec = XEC(m->status, xec_mask);  in decode_mc1_mce()
413 		bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58)));  in decode_mc1_mce()
548 static void decode_mc2_mce(struct mce *m)  in decode_mc2_mce()  argument
550 	u16 ec = EC(m->status);  in decode_mc2_mce()
551 	u8 xec = XEC(m->status, xec_mask);  in decode_mc2_mce()
559 static void decode_mc3_mce(struct mce *m)  in decode_mc3_mce()  argument
561 	u16 ec = EC(m->status);  in decode_mc3_mce()
562 	u8 xec = XEC(m->status, xec_mask);  in decode_mc3_mce()
588 static void decode_mc4_mce(struct mce *m)  in decode_mc4_mce()  argument
591 	int node_id = amd_get_nb_id(m->extcpu);  in decode_mc4_mce()
592 	u16 ec = EC(m->status);  in decode_mc4_mce()
593 	u8 xec = XEC(m->status, 0x1f);  in decode_mc4_mce()
610 				nb_bus_decoder(node_id, m);  in decode_mc4_mce()
646 static void decode_mc5_mce(struct mce *m)  in decode_mc5_mce()  argument
649 	u16 ec = EC(m->status);  in decode_mc5_mce()
650 	u8 xec = XEC(m->status, xec_mask);  in decode_mc5_mce()
678 static void decode_mc6_mce(struct mce *m)  in decode_mc6_mce()  argument
680 	u8 xec = XEC(m->status, xec_mask);  in decode_mc6_mce()
721 static bool amd_filter_mce(struct mce *m)  in amd_filter_mce()  argument
723 	u8 xec = (m->status >> 16) & 0x1f;  in amd_filter_mce()
728 	if (m->bank == 4 && xec == 0x5 && !report_gart_errors)  in amd_filter_mce()
734 static const char *decode_error_status(struct mce *m)  in decode_error_status()  argument
736 	if (m->status & MCI_STATUS_UC) {  in decode_error_status()
737 		if (m->status & MCI_STATUS_PCC)  in decode_error_status()
739 		if (m->mcgstatus & MCG_STATUS_RIPV)  in decode_error_status()
744 	if (m->status & MCI_STATUS_DEFERRED)  in decode_error_status()
752 	struct mce *m = (struct mce *)data;  in amd_decode_mce()  local
753 	struct cpuinfo_x86 *c = &cpu_data(m->extcpu);  in amd_decode_mce()
756 	if (amd_filter_mce(m))  in amd_decode_mce()
759 	pr_emerg(HW_ERR "%s\n", decode_error_status(m));  in amd_decode_mce()
762 		m->extcpu,  in amd_decode_mce()
764 		m->bank,  in amd_decode_mce()
765 		((m->status & MCI_STATUS_OVER)	? "Over"  : "-"),  in amd_decode_mce()
766 		((m->status & MCI_STATUS_UC)	? "UE"	  : "CE"),  in amd_decode_mce()
767 		((m->status & MCI_STATUS_MISCV)	? "MiscV" : "-"),  in amd_decode_mce()
768 		((m->status & MCI_STATUS_PCC)	? "PCC"	  : "-"),  in amd_decode_mce()
769 		((m->status & MCI_STATUS_ADDRV)	? "AddrV" : "-"));  in amd_decode_mce()
773 			((m->status & MCI_STATUS_DEFERRED) ? "Deferred" : "-"),  in amd_decode_mce()
774 			((m->status & MCI_STATUS_POISON)   ? "Poison"   : "-"));  in amd_decode_mce()
777 	ecc = (m->status >> 45) & 0x3;  in amd_decode_mce()
781 	pr_cont("]: 0x%016llx\n", m->status);  in amd_decode_mce()
783 	if (m->status & MCI_STATUS_ADDRV)  in amd_decode_mce()
784 		pr_emerg(HW_ERR "MC%d Error Address: 0x%016llx\n", m->bank, m->addr);  in amd_decode_mce()
789 	switch (m->bank) {  in amd_decode_mce()
791 		decode_mc0_mce(m);  in amd_decode_mce()
795 		decode_mc1_mce(m);  in amd_decode_mce()
799 		decode_mc2_mce(m);  in amd_decode_mce()
803 		decode_mc3_mce(m);  in amd_decode_mce()
807 		decode_mc4_mce(m);  in amd_decode_mce()
811 		decode_mc5_mce(m);  in amd_decode_mce()
815 		decode_mc6_mce(m);  in amd_decode_mce()
823 	amd_decode_err_code(m->status & 0xffff);  in amd_decode_mce()