96 	reg &= (pvt->model == 0x30) ? ~3 : ~1;  in f15h_select_dct()
143 		dct = (dct && pvt->model == 0x30) ? 3 : dct;  in amd64_read_dct_pci_cfg()
221 	if (pvt->fam == 0x15 && pvt->model < 0x10)  in set_scrub_rate()
234 	if (pvt->fam == 0x15 && pvt->model < 0x10)  in get_scrub_rate()
361 		  (pvt->fam == 0x15 && pvt->model >= 0x30)) {  in get_cs_base_and_mask()
768 	} else if (pvt->fam == 0x15 && pvt->model == 0x30) {  in prep_chip_selects()
845 		if (pvt->model < 0x60)  in determine_memory_type()
1012 	if (pvt->model == 0x60)  in read_dram_base_limit_regs()
1014 	else if (pvt->model == 0x30)  in read_dram_base_limit_regs()
1540 			if (pvt->fam == 0x15 && pvt->model >= 0x30) {  in f1x_lookup_addr_in_dct()
1564 		if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3))  in f1x_swap_interleaved_region()
1798 		if (pvt->fam == 0x15 && pvt->model >= 0x30)  in f1x_translate_sysaddr_to_cs()
2332 		if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25))  in read_mc_regs()
2704 	pvt->model	= boot_cpu_data.x86_model;  in per_family_init()
2719 		if (pvt->model == 0x30) {  in per_family_init()
2723 		} else if (pvt->model == 0x60) {  in per_family_init()
2734 		if (pvt->model == 0x30) {  in per_family_init()