350 	struct dma_device dma_dev[XGENE_DMA_MAX_CHANNEL];  member
1745 			       struct dma_device *dma_dev)  in xgene_dma_set_caps()  argument
1748 	dma_cap_zero(dma_dev->cap_mask);  in xgene_dma_set_caps()
1751 	dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);  in xgene_dma_set_caps()
1752 	dma_cap_set(DMA_SG, dma_dev->cap_mask);  in xgene_dma_set_caps()
1765 		dma_cap_set(DMA_PQ, dma_dev->cap_mask);  in xgene_dma_set_caps()
1766 		dma_cap_set(DMA_XOR, dma_dev->cap_mask);  in xgene_dma_set_caps()
1769 		dma_cap_set(DMA_XOR, dma_dev->cap_mask);  in xgene_dma_set_caps()
1773 	dma_dev->dev = chan->dev;  in xgene_dma_set_caps()
1774 	dma_dev->device_alloc_chan_resources = xgene_dma_alloc_chan_resources;  in xgene_dma_set_caps()
1775 	dma_dev->device_free_chan_resources = xgene_dma_free_chan_resources;  in xgene_dma_set_caps()
1776 	dma_dev->device_issue_pending = xgene_dma_issue_pending;  in xgene_dma_set_caps()
1777 	dma_dev->device_tx_status = xgene_dma_tx_status;  in xgene_dma_set_caps()
1778 	dma_dev->device_prep_dma_memcpy = xgene_dma_prep_memcpy;  in xgene_dma_set_caps()
1779 	dma_dev->device_prep_dma_sg = xgene_dma_prep_sg;  in xgene_dma_set_caps()
1781 	if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {  in xgene_dma_set_caps()
1782 		dma_dev->device_prep_dma_xor = xgene_dma_prep_xor;  in xgene_dma_set_caps()
1783 		dma_dev->max_xor = XGENE_DMA_MAX_XOR_SRC;  in xgene_dma_set_caps()
1784 		dma_dev->xor_align = XGENE_DMA_XOR_ALIGNMENT;  in xgene_dma_set_caps()
1787 	if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {  in xgene_dma_set_caps()
1788 		dma_dev->device_prep_dma_pq = xgene_dma_prep_pq;  in xgene_dma_set_caps()
1789 		dma_dev->max_pq = XGENE_DMA_MAX_XOR_SRC;  in xgene_dma_set_caps()
1790 		dma_dev->pq_align = XGENE_DMA_XOR_ALIGNMENT;  in xgene_dma_set_caps()
1797 	struct dma_device *dma_dev = &pdma->dma_dev[id];  in xgene_dma_async_register()  local
1800 	chan->dma_chan.device = dma_dev;  in xgene_dma_async_register()
1814 	xgene_dma_set_caps(chan, dma_dev);  in xgene_dma_async_register()
1817 	INIT_LIST_HEAD(&dma_dev->channels);  in xgene_dma_async_register()
1818 	list_add_tail(&chan->dma_chan.device_node, &dma_dev->channels);  in xgene_dma_async_register()
1821 	ret = dma_async_device_register(dma_dev);  in xgene_dma_async_register()
1832 		 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "MEMCPY " : "",  in xgene_dma_async_register()
1833 		 dma_has_cap(DMA_SG, dma_dev->cap_mask) ? "SGCPY " : "",  in xgene_dma_async_register()
1834 		 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "XOR " : "",  in xgene_dma_async_register()
1835 		 dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "PQ " : "");  in xgene_dma_async_register()
1848 				dma_async_device_unregister(&pdma->dma_dev[j]);  in xgene_dma_init_async()
1864 		dma_async_device_unregister(&pdma->dma_dev[i]);  in xgene_dma_async_unregister()