242 static inline void tdc_write(struct tegra_dma_channel *tdc,  in tdc_write()  function
383 		tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,  in tegra_dma_pause()
397 		tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0);  in tegra_dma_resume()
411 	tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);  in tegra_dma_stop()
415 	tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);  in tegra_dma_stop()
421 		tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);  in tegra_dma_stop()
431 	tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);  in tegra_dma_start()
432 	tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);  in tegra_dma_start()
433 	tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);  in tegra_dma_start()
434 	tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);  in tegra_dma_start()
435 	tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);  in tegra_dma_start()
437 		tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, ch_regs->wcount);  in tegra_dma_start()
440 	tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,  in tegra_dma_start()
475 	tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);  in tegra_dma_configure_for_next()
476 	tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);  in tegra_dma_configure_for_next()
478 		tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,  in tegra_dma_configure_for_next()
480 	tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,  in tegra_dma_configure_for_next()
670 		tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);  in tegra_dma_isr()
1573 		tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq);  in tegra_dma_pm_resume()
1574 		tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr);  in tegra_dma_pm_resume()
1575 		tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq);  in tegra_dma_pm_resume()
1576 		tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr);  in tegra_dma_pm_resume()
1577 		tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,  in tegra_dma_pm_resume()