268 				 flags, &sed->dma);  in ioat3_alloc_sed()
282 	dma_pool_free(device->sed_hw_pool[sed->hw_pool], sed->hw, sed->dma);  in ioat3_free_sed()
1009 		pq->sed_addr = desc->sed->dma;  in __ioat3_prep_pq16_lock()
1234 	struct dma_device *dma = &device->common;  in ioat_xor_val_self_test()  local
1239 	if (!dma_has_cap(DMA_XOR, dma->cap_mask))  in ioat_xor_val_self_test()
1273 	dma_chan = container_of(dma->channels.next, struct dma_chan,  in ioat_xor_val_self_test()
1275 	if (dma->device_alloc_chan_resources(dma_chan) < 1) {  in ioat_xor_val_self_test()
1295 	tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs,  in ioat_xor_val_self_test()
1315 	dma->device_issue_pending(dma_chan);  in ioat_xor_val_self_test()
1320 	    dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {  in ioat_xor_val_self_test()
1363 	tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,  in ioat_xor_val_self_test()
1382 	dma->device_issue_pending(dma_chan);  in ioat_xor_val_self_test()
1387 	    dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {  in ioat_xor_val_self_test()
1416 	tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,  in ioat_xor_val_self_test()
1435 	dma->device_issue_pending(dma_chan);  in ioat_xor_val_self_test()
1440 	    dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {  in ioat_xor_val_self_test()
1472 	dma->device_free_chan_resources(dma_chan);  in ioat_xor_val_self_test()
1580 	struct dma_device *dma;  in ioat3_intr_quirk()  local
1585 	dma = &device->common;  in ioat3_intr_quirk()
1592 		list_for_each_entry(c, &dma->channels, device_node) {  in ioat3_intr_quirk()
1608 	struct dma_device *dma;  in ioat3_dma_probe()  local
1618 	dma = &device->common;  in ioat3_dma_probe()
1619 	dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;  in ioat3_dma_probe()
1620 	dma->device_issue_pending = ioat2_issue_pending;  in ioat3_dma_probe()
1621 	dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;  in ioat3_dma_probe()
1622 	dma->device_free_chan_resources = ioat2_free_chan_resources;  in ioat3_dma_probe()
1624 	dma_cap_set(DMA_INTERRUPT, dma->cap_mask);  in ioat3_dma_probe()
1625 	dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock;  in ioat3_dma_probe()
1638 		dma->max_xor = 8;  in ioat3_dma_probe()
1640 		dma_cap_set(DMA_XOR, dma->cap_mask);  in ioat3_dma_probe()
1641 		dma->device_prep_dma_xor = ioat3_prep_xor;  in ioat3_dma_probe()
1643 		dma_cap_set(DMA_XOR_VAL, dma->cap_mask);  in ioat3_dma_probe()
1644 		dma->device_prep_dma_xor_val = ioat3_prep_xor_val;  in ioat3_dma_probe()
1650 		dma->device_prep_dma_pq = ioat3_prep_pq;  in ioat3_dma_probe()
1651 		dma->device_prep_dma_pq_val = ioat3_prep_pq_val;  in ioat3_dma_probe()
1652 		dma_cap_set(DMA_PQ, dma->cap_mask);  in ioat3_dma_probe()
1653 		dma_cap_set(DMA_PQ_VAL, dma->cap_mask);  in ioat3_dma_probe()
1656 			dma_set_maxpq(dma, 16, 0);  in ioat3_dma_probe()
1658 			dma_set_maxpq(dma, 8, 0);  in ioat3_dma_probe()
1662 			dma->device_prep_dma_xor = ioat3_prep_pqxor;  in ioat3_dma_probe()
1663 			dma->device_prep_dma_xor_val = ioat3_prep_pqxor_val;  in ioat3_dma_probe()
1664 			dma_cap_set(DMA_XOR, dma->cap_mask);  in ioat3_dma_probe()
1665 			dma_cap_set(DMA_XOR_VAL, dma->cap_mask);  in ioat3_dma_probe()
1668 				dma->max_xor = 16;  in ioat3_dma_probe()
1670 				dma->max_xor = 8;  in ioat3_dma_probe()
1675 	dma->device_tx_status = ioat3_tx_status;  in ioat3_dma_probe()
1701 	list_for_each_entry(c, &dma->channels, device_node) {  in ioat3_dma_probe()