122 	void __iomem		*dca_base;  member
161 			writew(id, ioatdca->dca_base + (i * 4));  in ioat_dca_add_requester()
163 			writeb(0, ioatdca->dca_base + (i * 4) + 2);  in ioat_dca_add_requester()
185 			writew(0, ioatdca->dca_base + (i * 4));  in ioat_dca_remove_requester()
295 	ioatdca->dca_base = iobase + 0x54;  in ioat_dca_init()
335 			      readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET);  in ioat2_dca_add_requester()
361 			      readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET);  in ioat2_dca_remove_requester()
439 	ioatdca->dca_base = iobase + dca_offset;  in ioat2_dca_init()
443 	csi_fsb_control = readw(ioatdca->dca_base + IOAT_FSB_CAP_ENABLE_OFFSET);  in ioat2_dca_init()
447 		       ioatdca->dca_base + IOAT_FSB_CAP_ENABLE_OFFSET);  in ioat2_dca_init()
449 	pcie_control = readw(ioatdca->dca_base + IOAT_PCI_CAP_ENABLE_OFFSET);  in ioat2_dca_init()
453 		       ioatdca->dca_base + IOAT_PCI_CAP_ENABLE_OFFSET);  in ioat2_dca_init()
460 	tag_map = readl(ioatdca->dca_base + IOAT_APICID_TAG_MAP_OFFSET);  in ioat2_dca_init()
511 			      readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET);  in ioat3_dca_add_requester()
537 			      readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET);  in ioat3_dca_remove_requester()
660 	ioatdca->dca_base = iobase + dca_offset;  in ioat3_dca_init()
664 	csi_fsb_control = readw(ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET);  in ioat3_dca_init()
668 		       ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET);  in ioat3_dca_init()
670 	pcie_control = readw(ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET);  in ioat3_dca_init()
674 		       ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET);  in ioat3_dca_init()
682 		readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_LOW);  in ioat3_dca_init()
684 		readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_HIGH);  in ioat3_dca_init()