264 static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)  in imx_dmav1_readl()  function
304 		 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),  in imxdma_sg_next()
305 		 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),  in imxdma_sg_next()
306 		 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));  in imxdma_sg_next()
323 	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &  in imxdma_enable_hw()
325 	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |  in imxdma_enable_hw()
334 			tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));  in imxdma_enable_hw()
355 	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |  in imxdma_disable_hw()
357 	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &  in imxdma_disable_hw()
384 	disr = imx_dmav1_readl(imxdma, DMA_DISR);  in imxdma_err_handler()
386 	err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |  in imxdma_err_handler()
387 		   imx_dmav1_readl(imxdma, DMA_DRTOSR) |  in imxdma_err_handler()
388 		   imx_dmav1_readl(imxdma, DMA_DSESR)  |  in imxdma_err_handler()
389 		   imx_dmav1_readl(imxdma, DMA_DBOSR);  in imxdma_err_handler()
401 		if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {  in imxdma_err_handler()
405 		if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {  in imxdma_err_handler()
409 		if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {  in imxdma_err_handler()
413 		if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {  in imxdma_err_handler()
455 			tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));  in dma_irq_handle_channel()
501 	disr = imx_dmav1_readl(imxdma, DMA_DISR);  in dma_irq_handler()