Lines Matching refs:cpu_to_be32
267 #define DESC_HDR_DONE cpu_to_be32(0xff000000)
268 #define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
269 #define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
270 #define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
273 #define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
274 #define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
275 #define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
276 #define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
277 #define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
278 #define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
279 #define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
280 #define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
281 #define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
282 #define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
285 #define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
286 #define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
287 #define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
288 #define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
289 #define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000)
290 #define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
291 #define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
292 #define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
293 #define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000)
294 #define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
295 #define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
296 #define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
297 #define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000)
298 #define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000)
307 #define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
308 #define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
309 #define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
310 #define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
313 #define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
314 #define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
315 #define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
316 #define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
317 #define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300)
318 #define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
319 #define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
320 #define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
321 #define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000)
322 #define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200)
337 #define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
340 #define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
343 #define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
344 #define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
345 #define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
346 #define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)