839 	unsigned int ctxarb_ctl, ctx_enables;  in qat_hal_exec_micro_inst()  local
857 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_exec_micro_inst()
858 	ctx_enables &= IGNORE_W1C_MASK;  in qat_hal_exec_micro_inst()
867 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_exec_micro_inst()
913 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_exec_micro_inst()
924 	unsigned int ctxarb_cntl, ustore_addr, ctx_enables;  in qat_hal_rd_rel_reg()  local
944 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_rd_rel_reg()
945 	ctx_enables &= IGNORE_W1C_MASK;  in qat_hal_rd_rel_reg()
950 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_rd_rel_reg()
974 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_rd_rel_reg()
1141 	unsigned int ctx_enables;  in qat_hal_put_rel_rd_xfer()  local
1145 	status = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_put_rel_rd_xfer()
1146 	if (CE_INUSE_CONTEXTS & ctx_enables) {  in qat_hal_put_rel_rd_xfer()
1180 	unsigned int gprval, ctx_enables;  in qat_hal_put_rel_wr_xfer()  local
1195 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_put_rel_wr_xfer()
1196 	if (CE_INUSE_CONTEXTS & ctx_enables) {  in qat_hal_put_rel_wr_xfer()
1236 	unsigned int ctx_enables;  in qat_hal_put_rel_nn()  local
1239 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_put_rel_nn()
1240 	ctx_enables &= IGNORE_W1C_MASK;  in qat_hal_put_rel_nn()
1241 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables | CE_NN_MODE);  in qat_hal_put_rel_nn()
1244 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_put_rel_nn()
1254 	unsigned int ctx_enables;  in qat_hal_convert_abs_to_rel()  local
1256 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_convert_abs_to_rel()
1257 	if (ctx_enables & CE_INUSE_CONTEXTS) {  in qat_hal_convert_abs_to_rel()