326 				unsigned int ae_csr, unsigned int csr_val)  in qat_hal_wr_indr_csr()  argument
336 		qat_hal_wr_ae_csr(handle, ae, ae_csr, csr_val);  in qat_hal_wr_indr_csr()
344 				unsigned int ae_csr, unsigned int *csr_val)  in qat_hal_rd_indr_csr()  argument
350 	qat_hal_rd_ae_csr(handle, ae, ae_csr, csr_val);  in qat_hal_rd_indr_csr()
445 	unsigned int csr_val, times = 30;  in qat_hal_init_esram()  local
447 	csr_val = ADF_CSR_RD(csr_addr, 0);  in qat_hal_init_esram()
448 	if ((csr_val & ESRAM_AUTO_TINIT) && (csr_val & ESRAM_AUTO_TINIT_DONE))  in qat_hal_init_esram()
451 	csr_val = ADF_CSR_RD(csr_addr, 0);  in qat_hal_init_esram()
452 	csr_val |= ESRAM_AUTO_TINIT;  in qat_hal_init_esram()
453 	ADF_CSR_WR(csr_addr, 0, csr_val);  in qat_hal_init_esram()
457 		csr_val = ADF_CSR_RD(csr_addr, 0);  in qat_hal_init_esram()
458 	} while (!(csr_val & ESRAM_AUTO_TINIT_DONE) && times--);  in qat_hal_init_esram()
606 	unsigned int csr_val = 0;  in qat_hal_clear_gpr()  local
620 		qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL, &csr_val);  in qat_hal_clear_gpr()
621 		csr_val &= ~(1 << MMC_SHARE_CS_BITPOS);  in qat_hal_clear_gpr()
622 		qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val);  in qat_hal_clear_gpr()
623 		qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr_val);  in qat_hal_clear_gpr()
624 		csr_val &= IGNORE_W1C_MASK;  in qat_hal_clear_gpr()
625 		csr_val |= CE_NN_MODE;  in qat_hal_clear_gpr()
626 		qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, csr_val);  in qat_hal_clear_gpr()
728 		unsigned int csr_val = 0;  in qat_hal_init()  local
732 		qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE, &csr_val);  in qat_hal_init()
733 		csr_val |= 0x1;  in qat_hal_init()
734 		qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val);  in qat_hal_init()
836 	unsigned int csr_val = 0, newcsr_val;  in qat_hal_exec_micro_inst()  local
894 	qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL, &csr_val);  in qat_hal_exec_micro_inst()
895 	newcsr_val = CLR_BIT(csr_val, MMC_SHARE_CS_BITPOS);  in qat_hal_exec_micro_inst()