78 #define AE(handle, ae) handle->hal_handle->aes[ae]  argument
112 			  unsigned char ae, unsigned int ctx_mask)  in qat_hal_set_live_ctx()  argument
114 	AE(handle, ae).live_ctx_mask = ctx_mask;  in qat_hal_set_live_ctx()
119 			     unsigned char ae, unsigned int csr,  in qat_hal_rd_ae_csr()  argument
125 		*value = GET_AE_CSR(handle, ae, csr);  in qat_hal_rd_ae_csr()
126 		if (!(GET_AE_CSR(handle, ae, LOCAL_CSR_STATUS) & LCS_STATUS))  in qat_hal_rd_ae_csr()
135 			     unsigned char ae, unsigned int csr,  in qat_hal_wr_ae_csr()  argument
141 		SET_AE_CSR(handle, ae, csr, value);  in qat_hal_wr_ae_csr()
142 		if (!(GET_AE_CSR(handle, ae, LOCAL_CSR_STATUS) & LCS_STATUS))  in qat_hal_wr_ae_csr()
151 				     unsigned char ae, unsigned char ctx,  in qat_hal_get_wakeup_event()  argument
156 	qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx);  in qat_hal_get_wakeup_event()
157 	qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx);  in qat_hal_get_wakeup_event()
158 	qat_hal_rd_ae_csr(handle, ae, CTX_WAKEUP_EVENTS_INDIRECT, events);  in qat_hal_get_wakeup_event()
159 	qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx);  in qat_hal_get_wakeup_event()
163 			       unsigned char ae, unsigned int cycles,  in qat_hal_wait_cycles()  argument
171 	qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT, &base_cnt);  in qat_hal_wait_cycles()
175 			qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &csr);  in qat_hal_wait_cycles()
177 		qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT, &cur_cnt);  in qat_hal_wait_cycles()
199 			    unsigned char ae, unsigned char mode)  in qat_hal_set_ae_ctx_mode()  argument
209 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr);  in qat_hal_set_ae_ctx_mode()
214 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr);  in qat_hal_set_ae_ctx_mode()
219 			   unsigned char ae, unsigned char mode)  in qat_hal_set_ae_nn_mode()  argument
223 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr);  in qat_hal_set_ae_nn_mode()
231 		qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr);  in qat_hal_set_ae_nn_mode()
237 			   unsigned char ae, enum icp_qat_uof_regtype lm_type,  in qat_hal_set_ae_lm_mode()  argument
242 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr);  in qat_hal_set_ae_lm_mode()
261 		qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr);  in qat_hal_set_ae_lm_mode()
325 				unsigned char ae, unsigned int ctx_mask,  in qat_hal_wr_indr_csr()  argument
330 	qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx);  in qat_hal_wr_indr_csr()
335 		qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx);  in qat_hal_wr_indr_csr()
336 		qat_hal_wr_ae_csr(handle, ae, ae_csr, csr_val);  in qat_hal_wr_indr_csr()
339 	qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx);  in qat_hal_wr_indr_csr()
343 				unsigned char ae, unsigned char ctx,  in qat_hal_rd_indr_csr()  argument
348 	qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx);  in qat_hal_rd_indr_csr()
349 	qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx);  in qat_hal_rd_indr_csr()
350 	qat_hal_rd_ae_csr(handle, ae, ae_csr, csr_val);  in qat_hal_rd_indr_csr()
351 	qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx);  in qat_hal_rd_indr_csr()
355 				  unsigned char ae, unsigned int ctx_mask,  in qat_hal_put_sig_event()  argument
360 	qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx);  in qat_hal_put_sig_event()
364 		qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx);  in qat_hal_put_sig_event()
365 		qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_INDIRECT, events);  in qat_hal_put_sig_event()
367 	qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx);  in qat_hal_put_sig_event()
371 				     unsigned char ae, unsigned int ctx_mask,  in qat_hal_put_wakeup_event()  argument
376 	qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx);  in qat_hal_put_wakeup_event()
380 		qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx);  in qat_hal_put_wakeup_event()
381 		qat_hal_wr_ae_csr(handle, ae, CTX_WAKEUP_EVENTS_INDIRECT,  in qat_hal_put_wakeup_event()
384 	qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx);  in qat_hal_put_wakeup_event()
390 	unsigned char ae;  in qat_hal_check_ae_alive()  local
393 	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {  in qat_hal_check_ae_alive()
394 		if (!(handle->hal_handle->ae_mask & (1 << ae)))  in qat_hal_check_ae_alive()
397 		qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT,  in qat_hal_check_ae_alive()
402 			qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT,  in qat_hal_check_ae_alive()
408 			pr_err("QAT: AE%d is inactive!!\n", ae);  in qat_hal_check_ae_alive()
419 	unsigned char ae;  in qat_hal_reset_timestamp()  local
427 	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {  in qat_hal_reset_timestamp()
428 		if (!(handle->hal_handle->ae_mask & (1 << ae)))  in qat_hal_reset_timestamp()
430 		qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_LOW, 0);  in qat_hal_reset_timestamp()
431 		qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_HIGH, 0);  in qat_hal_reset_timestamp()
470 	unsigned char ae;  in qat_hal_clr_reset()  local
495 	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {  in qat_hal_clr_reset()
496 		if (!(handle->hal_handle->ae_mask & (1 << ae)))  in qat_hal_clr_reset()
498 		qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES,  in qat_hal_clr_reset()
500 		qat_hal_wr_indr_csr(handle, ae, ICP_QAT_UCLO_AE_ALL_CTX,  in qat_hal_clr_reset()
504 		qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, INIT_CTX_ARB_VALUE);  in qat_hal_clr_reset()
505 		qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, INIT_CCENABLE_VALUE);  in qat_hal_clr_reset()
506 		qat_hal_put_wakeup_event(handle, ae,  in qat_hal_clr_reset()
509 		qat_hal_put_sig_event(handle, ae,  in qat_hal_clr_reset()
526 				unsigned char ae, unsigned int ctx_mask)  in qat_hal_disable_ctx()  argument
530 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx);  in qat_hal_disable_ctx()
533 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx);  in qat_hal_disable_ctx()
567 		       unsigned char ae, unsigned int uaddr,  in qat_hal_wr_uwords()  argument
573 	qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS, &ustore_addr);  in qat_hal_wr_uwords()
575 	qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr);  in qat_hal_wr_uwords()
583 		qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo);  in qat_hal_wr_uwords()
584 		qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi);  in qat_hal_wr_uwords()
586 	qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr);  in qat_hal_wr_uwords()
590 			       unsigned char ae, unsigned int ctx_mask)  in qat_hal_enable_ctx()  argument
594 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx);  in qat_hal_enable_ctx()
598 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx);  in qat_hal_enable_ctx()
603 	unsigned char ae;  in qat_hal_clear_gpr()  local
611 	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {  in qat_hal_clear_gpr()
612 		if (!(handle->hal_handle->ae_mask & (1 << ae)))  in qat_hal_clear_gpr()
615 			qat_hal_init_rd_xfer(handle, ae, 0, ICP_SR_RD_ABS,  in qat_hal_clear_gpr()
617 			qat_hal_init_rd_xfer(handle, ae, 0, ICP_DR_RD_ABS,  in qat_hal_clear_gpr()
620 		qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL, &csr_val);  in qat_hal_clear_gpr()
622 		qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val);  in qat_hal_clear_gpr()
623 		qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr_val);  in qat_hal_clear_gpr()
626 		qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, csr_val);  in qat_hal_clear_gpr()
627 		qat_hal_wr_uwords(handle, ae, 0, ARRAY_SIZE(inst),  in qat_hal_clear_gpr()
629 		qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT,  in qat_hal_clear_gpr()
632 		qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &savctx);  in qat_hal_clear_gpr()
633 		qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, 0);  in qat_hal_clear_gpr()
634 		qat_hal_put_wakeup_event(handle, ae, ctx_mask, XCWE_VOLUNTARY);  in qat_hal_clear_gpr()
635 		qat_hal_wr_indr_csr(handle, ae, ctx_mask,  in qat_hal_clear_gpr()
637 		qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0);  in qat_hal_clear_gpr()
638 		qat_hal_enable_ctx(handle, ae, ctx_mask);  in qat_hal_clear_gpr()
640 	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {  in qat_hal_clear_gpr()
641 		if (!(handle->hal_handle->ae_mask & (1 << ae)))  in qat_hal_clear_gpr()
645 			ret = qat_hal_wait_cycles(handle, ae, 20, 1);  in qat_hal_clear_gpr()
649 			pr_err("QAT: clear GPR of AE %d failed", ae);  in qat_hal_clear_gpr()
652 		qat_hal_disable_ctx(handle, ae, ctx_mask);  in qat_hal_clear_gpr()
653 		qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS,  in qat_hal_clear_gpr()
655 		qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES,  in qat_hal_clear_gpr()
657 		qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT,  in qat_hal_clear_gpr()
660 		qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, INIT_CTX_ARB_VALUE);  in qat_hal_clear_gpr()
661 		qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, INIT_CCENABLE_VALUE);  in qat_hal_clear_gpr()
662 		qat_hal_put_wakeup_event(handle, ae, ctx_mask,  in qat_hal_clear_gpr()
664 		qat_hal_put_sig_event(handle, ae, ctx_mask,  in qat_hal_clear_gpr()
677 	unsigned char ae;  in qat_hal_init()  local
706 	for (ae = 0; ae < ICP_QAT_UCLO_MAX_AE; ae++) {  in qat_hal_init()
707 		if (!(hw_data->ae_mask & (1 << ae)))  in qat_hal_init()
709 		handle->hal_handle->aes[ae].free_addr = 0;  in qat_hal_init()
710 		handle->hal_handle->aes[ae].free_size =  in qat_hal_init()
712 		handle->hal_handle->aes[ae].ustore_size =  in qat_hal_init()
714 		handle->hal_handle->aes[ae].live_ctx_mask =  in qat_hal_init()
716 		max_en_ae_id = ae;  in qat_hal_init()
727 	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {  in qat_hal_init()
730 		if (!(hw_data->ae_mask & (1 << ae)))  in qat_hal_init()
732 		qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE, &csr_val);  in qat_hal_init()
734 		qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val);  in qat_hal_init()
754 void qat_hal_start(struct icp_qat_fw_loader_handle *handle, unsigned char ae,  in qat_hal_start()  argument
757 	qat_hal_put_wakeup_event(handle, ae, (~ctx_mask) &  in qat_hal_start()
759 	qat_hal_enable_ctx(handle, ae, ctx_mask);  in qat_hal_start()
762 void qat_hal_stop(struct icp_qat_fw_loader_handle *handle, unsigned char ae,  in qat_hal_stop()  argument
765 	qat_hal_disable_ctx(handle, ae, ctx_mask);  in qat_hal_stop()
769 		    unsigned char ae, unsigned int ctx_mask, unsigned int upc)  in qat_hal_set_pc()  argument
771 	qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT,  in qat_hal_set_pc()
776 			       unsigned char ae, unsigned int uaddr,  in qat_hal_get_uwords()  argument
782 	qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL, &misc_control);  in qat_hal_get_uwords()
783 	qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL,  in qat_hal_get_uwords()
785 	qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS, &ustore_addr);  in qat_hal_get_uwords()
788 		qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr);  in qat_hal_get_uwords()
790 		qat_hal_rd_ae_csr(handle, ae, USTORE_DATA_LOWER, &uwrd_lo);  in qat_hal_get_uwords()
791 		qat_hal_rd_ae_csr(handle, ae, USTORE_DATA_UPPER, &uwrd_hi);  in qat_hal_get_uwords()
795 	qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, misc_control);  in qat_hal_get_uwords()
796 	qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr);  in qat_hal_get_uwords()
800 		     unsigned char ae, unsigned int uaddr,  in qat_hal_wr_umem()  argument
805 	qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS, &ustore_addr);  in qat_hal_wr_umem()
807 	qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr);  in qat_hal_wr_umem()
818 		qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo);  in qat_hal_wr_umem()
819 		qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi);  in qat_hal_wr_umem()
821 	qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr);  in qat_hal_wr_umem()
826 				   unsigned char ae, unsigned char ctx,  in qat_hal_exec_micro_inst()  argument
846 	qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_0_INDIRECT, &ind_lm_addr0);  in qat_hal_exec_micro_inst()
847 	qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_1_INDIRECT, &ind_lm_addr1);  in qat_hal_exec_micro_inst()
848 	qat_hal_rd_indr_csr(handle, ae, ctx, INDIRECT_LM_ADDR_0_BYTE_INDEX,  in qat_hal_exec_micro_inst()
850 	qat_hal_rd_indr_csr(handle, ae, ctx, INDIRECT_LM_ADDR_1_BYTE_INDEX,  in qat_hal_exec_micro_inst()
853 		qat_hal_get_uwords(handle, ae, 0, inst_num, savuwords);  in qat_hal_exec_micro_inst()
854 	qat_hal_get_wakeup_event(handle, ae, ctx, &wakeup_events);  in qat_hal_exec_micro_inst()
855 	qat_hal_rd_indr_csr(handle, ae, ctx, CTX_STS_INDIRECT, &savpc);  in qat_hal_exec_micro_inst()
857 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_exec_micro_inst()
859 	qat_hal_rd_ae_csr(handle, ae, CC_ENABLE, &savcc);  in qat_hal_exec_micro_inst()
860 	qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &savctx);  in qat_hal_exec_micro_inst()
861 	qat_hal_rd_ae_csr(handle, ae, CTX_ARB_CNTL, &ctxarb_ctl);  in qat_hal_exec_micro_inst()
862 	qat_hal_rd_indr_csr(handle, ae, ctx, FUTURE_COUNT_SIGNAL_INDIRECT,  in qat_hal_exec_micro_inst()
864 	qat_hal_rd_indr_csr(handle, ae, ctx, CTX_SIG_EVENTS_INDIRECT, &ind_sig);  in qat_hal_exec_micro_inst()
865 	qat_hal_rd_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, &act_sig);  in qat_hal_exec_micro_inst()
867 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_exec_micro_inst()
868 	qat_hal_wr_uwords(handle, ae, 0, inst_num, micro_inst);  in qat_hal_exec_micro_inst()
869 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_STS_INDIRECT, 0);  in qat_hal_exec_micro_inst()
870 	qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, ctx & ACS_ACNO);  in qat_hal_exec_micro_inst()
872 		qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, savcc & 0xffffdfff);  in qat_hal_exec_micro_inst()
873 	qat_hal_put_wakeup_event(handle, ae, (1 << ctx), XCWE_VOLUNTARY);  in qat_hal_exec_micro_inst()
874 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_SIG_EVENTS_INDIRECT, 0);  in qat_hal_exec_micro_inst()
875 	qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0);  in qat_hal_exec_micro_inst()
876 	qat_hal_enable_ctx(handle, ae, (1 << ctx));  in qat_hal_exec_micro_inst()
878 	if (qat_hal_wait_cycles(handle, ae, max_cycle, 1) != 0)  in qat_hal_exec_micro_inst()
883 		qat_hal_rd_indr_csr(handle, ae, ctx, CTX_STS_INDIRECT,  in qat_hal_exec_micro_inst()
888 	qat_hal_disable_ctx(handle, ae, (1 << ctx));  in qat_hal_exec_micro_inst()
890 		qat_hal_wr_uwords(handle, ae, 0, inst_num, savuwords);  in qat_hal_exec_micro_inst()
891 	qat_hal_put_wakeup_event(handle, ae, (1 << ctx), wakeup_events);  in qat_hal_exec_micro_inst()
892 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_STS_INDIRECT,  in qat_hal_exec_micro_inst()
894 	qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL, &csr_val);  in qat_hal_exec_micro_inst()
896 	qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, newcsr_val);  in qat_hal_exec_micro_inst()
897 	qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, savcc);  in qat_hal_exec_micro_inst()
898 	qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, savctx & ACS_ACNO);  in qat_hal_exec_micro_inst()
899 	qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, ctxarb_ctl);  in qat_hal_exec_micro_inst()
900 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx),  in qat_hal_exec_micro_inst()
902 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx),  in qat_hal_exec_micro_inst()
904 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx),  in qat_hal_exec_micro_inst()
906 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx),  in qat_hal_exec_micro_inst()
908 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx),  in qat_hal_exec_micro_inst()
910 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx),  in qat_hal_exec_micro_inst()
912 	qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, act_sig);  in qat_hal_exec_micro_inst()
913 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_exec_micro_inst()
919 			      unsigned char ae, unsigned char ctx,  in qat_hal_rd_rel_reg()  argument
942 	qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &savctx);  in qat_hal_rd_rel_reg()
943 	qat_hal_rd_ae_csr(handle, ae, CTX_ARB_CNTL, &ctxarb_cntl);  in qat_hal_rd_rel_reg()
944 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_rd_rel_reg()
947 		qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS,  in qat_hal_rd_rel_reg()
949 	qat_hal_get_uwords(handle, ae, 0, 1, &savuword);  in qat_hal_rd_rel_reg()
950 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_rd_rel_reg()
951 	qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS, &ustore_addr);  in qat_hal_rd_rel_reg()
953 	qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr);  in qat_hal_rd_rel_reg()
957 	qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo);  in qat_hal_rd_rel_reg()
958 	qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi);  in qat_hal_rd_rel_reg()
959 	qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr);  in qat_hal_rd_rel_reg()
961 	qat_hal_wait_cycles(handle, ae, 0x8, 0);  in qat_hal_rd_rel_reg()
967 	qat_hal_rd_ae_csr(handle, ae, ALU_OUT, data);  in qat_hal_rd_rel_reg()
968 	qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr);  in qat_hal_rd_rel_reg()
969 	qat_hal_wr_uwords(handle, ae, 0, 1, &savuword);  in qat_hal_rd_rel_reg()
971 		qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS,  in qat_hal_rd_rel_reg()
973 	qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, ctxarb_cntl);  in qat_hal_rd_rel_reg()
974 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_rd_rel_reg()
980 			      unsigned char ae, unsigned char ctx,  in qat_hal_wr_rel_reg()  argument
1022 	return qat_hal_exec_micro_inst(handle, ae, ctx, insts, num_inst,  in qat_hal_wr_rel_reg()
1062 				      unsigned char ae, unsigned char ctx,  in qat_hal_exec_micro_init_lm()  argument
1071 		qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0, &gpra0);  in qat_hal_exec_micro_init_lm()
1072 		qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x1, &gpra1);  in qat_hal_exec_micro_init_lm()
1073 		qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x2, &gpra2);  in qat_hal_exec_micro_init_lm()
1074 		qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0, &gprb0);  in qat_hal_exec_micro_init_lm()
1075 		qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0x1, &gprb1);  in qat_hal_exec_micro_init_lm()
1078 	stat = qat_hal_exec_micro_inst(handle, ae, ctx, micro_inst, inst_num, 1,  in qat_hal_exec_micro_init_lm()
1082 	qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0, gpra0);  in qat_hal_exec_micro_init_lm()
1083 	qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x1, gpra1);  in qat_hal_exec_micro_init_lm()
1084 	qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x2, gpra2);  in qat_hal_exec_micro_init_lm()
1085 	qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0, gprb0);  in qat_hal_exec_micro_init_lm()
1086 	qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0x1, gprb1);  in qat_hal_exec_micro_init_lm()
1092 			unsigned char ae,  in qat_hal_batch_wr_lm()  argument
1114 		ae = plm_init->ae;  in qat_hal_batch_wr_lm()
1126 		stat = qat_hal_exec_micro_init_lm(handle, ae, 0, &first_exec,  in qat_hal_batch_wr_lm()
1135 				   unsigned char ae, unsigned char ctx,  in qat_hal_put_rel_rd_xfer()  argument
1145 	status = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_put_rel_rd_xfer()
1162 		SET_AE_XFER(handle, ae, reg_addr, val);  in qat_hal_put_rel_rd_xfer()
1166 		SET_AE_XFER(handle, ae, (reg_addr + dr_offset), val);  in qat_hal_put_rel_rd_xfer()
1176 				   unsigned char ae, unsigned char ctx,  in qat_hal_put_rel_wr_xfer()  argument
1195 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_put_rel_wr_xfer()
1212 	qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, gprnum, &gprval);  in qat_hal_put_rel_wr_xfer()
1226 	status = qat_hal_exec_micro_inst(handle, ae, ctx, micro_inst, num_inst,  in qat_hal_put_rel_wr_xfer()
1228 	qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, gprnum, gprval);  in qat_hal_put_rel_wr_xfer()
1233 			      unsigned char ae, unsigned char ctx,  in qat_hal_put_rel_nn()  argument
1239 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_put_rel_nn()
1241 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables | CE_NN_MODE);  in qat_hal_put_rel_nn()
1243 	stat = qat_hal_put_rel_wr_xfer(handle, ae, ctx, ICP_NEIGH_REL, nn, val);  in qat_hal_put_rel_nn()
1244 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_put_rel_nn()
1249 				      *handle, unsigned char ae,  in qat_hal_convert_abs_to_rel()  argument
1256 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_convert_abs_to_rel()
1270 		     unsigned char ae, unsigned char ctx_mask,  in qat_hal_init_gpr()  argument
1284 			qat_hal_convert_abs_to_rel(handle, ae, reg_num, &reg,  in qat_hal_init_gpr()
1293 		stat = qat_hal_wr_rel_reg(handle, ae, ctx, type, reg, regdata);  in qat_hal_init_gpr()
1304 			 unsigned char ae, unsigned char ctx_mask,  in qat_hal_init_wr_xfer()  argument
1318 			qat_hal_convert_abs_to_rel(handle, ae, reg_num, &reg,  in qat_hal_init_wr_xfer()
1327 		stat = qat_hal_put_rel_wr_xfer(handle, ae, ctx, type, reg,  in qat_hal_init_wr_xfer()
1339 			 unsigned char ae, unsigned char ctx_mask,  in qat_hal_init_rd_xfer()  argument
1353 			qat_hal_convert_abs_to_rel(handle, ae, reg_num, &reg,  in qat_hal_init_rd_xfer()
1362 		stat = qat_hal_put_rel_rd_xfer(handle, ae, ctx, type, reg,  in qat_hal_init_rd_xfer()
1374 		    unsigned char ae, unsigned char ctx_mask,  in qat_hal_init_nn()  argument
1386 		stat = qat_hal_put_rel_nn(handle, ae, ctx, reg_num, regdata);  in qat_hal_init_nn()