Lines Matching refs:HIFN_1_DMA_CSR
196 #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ macro
718 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_stop_device()
1047 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_init_registers()
1061 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_init_registers()
1075 hifn_read_1(dev, HIFN_1_DMA_CSR); in hifn_init_registers()
1274 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); in hifn_setup_cmd_desc()
1309 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); in hifn_setup_src_desc()
1336 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); in hifn_setup_res_desc()
1365 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); in hifn_setup_dst_desc()
1912 hifn_write_1(dev, HIFN_1_DMA_CSR, r); in hifn_work()
1960 dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR); in hifn_interrupt()
1971 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg); in hifn_interrupt()
1989 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER | in hifn_interrupt()