Lines Matching refs:u32
90 wr_reg32((u32 __iomem *)reg, (data & 0xffffffff00000000ull) >> 32); in wr_reg64()
91 wr_reg32((u32 __iomem *)reg + 1, data & 0x00000000ffffffffull); in wr_reg64()
96 return (((u64)rd_reg32((u32 __iomem *)reg)) << 32) | in rd_reg64()
97 ((u64)rd_reg32((u32 __iomem *)reg + 1)); in rd_reg64()
103 wr_reg32((u32 __iomem *)reg + 1, (data & 0xffffffff00000000ull) >> 32); in wr_reg64()
104 wr_reg32((u32 __iomem *)reg, data & 0x00000000ffffffffull); in wr_reg64()
109 return (((u64)rd_reg32((u32 __iomem *)reg + 1)) << 32) | in rd_reg64()
110 ((u64)rd_reg32((u32 __iomem *)reg)); in rd_reg64()
122 u32 jrstatus; /* Status for completed descriptor */
191 u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/
192 u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/
199 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */
200 u32 comp_parms_ls; /* CTPR - Compile Parameters Register */
205 u32 faultliodn; /* FALR - Fault Address LIODN */
206 u32 faultdetail; /* FADR - Fault Addr Detail */
207 u32 rsvd2;
208 u32 status; /* CSTA - CAAM Status */
212 u32 rtic_id; /* RVID - RTIC Version ID */
213 u32 ccb_id; /* CCBVID - CCB Version ID */
214 u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/
215 u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/
216 u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */
217 u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/
218 u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */
219 u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */
228 u32 liodn_ms; /* lock and make-trusted control bits */
229 u32 liodn_ls; /* LIODN for non-sequence and seq access */
234 u32 rsvd1;
235 u32 pidr; /* partition ID, DECO */
241 u32 mode; /* RTSTMODEx - Test mode */
242 u32 rsvd1[3];
243 u32 reset; /* RTSTRESETx - Test reset control */
244 u32 rsvd2[3];
245 u32 status; /* RTSTSSTATUSx - Test status */
246 u32 rsvd3;
247 u32 errstat; /* RTSTERRSTATx - Test error status */
248 u32 rsvd4;
249 u32 errctl; /* RTSTERRCTLx - Test error control */
250 u32 rsvd5;
251 u32 entropy; /* RTSTENTROPYx - Test entropy */
252 u32 rsvd6[15];
253 u32 verifctl; /* RTSTVERIFCTLx - Test verification control */
254 u32 rsvd7;
255 u32 verifstat; /* RTSTVERIFSTATx - Test verification status */
256 u32 rsvd8;
257 u32 verifdata; /* RTSTVERIFDx - Test verification data */
258 u32 rsvd9;
259 u32 xkey; /* RTSTXKEYx - Test XKEY */
260 u32 rsvd10;
261 u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */
262 u32 rsvd11;
263 u32 oscct; /* RTSTOSCCTx - Test oscillator counter */
264 u32 rsvd12;
265 u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */
266 u32 rsvd13[2];
267 u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */
268 u32 rsvd14[15];
284 u32 rtmctl; /* misc. control register */
285 u32 rtscmisc; /* statistical check misc. register */
286 u32 rtpkrrng; /* poker range register */
288 u32 rtpkrmax; /* PRGM=1: poker max. limit register */
289 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
295 u32 rtsdctl; /* seed control register */
297 u32 rtsblim; /* PRGM=1: sparse bit limit register */
298 u32 rttotsam; /* PRGM=0: total samples register */
300 u32 rtfrqmin; /* frequency count min. limit register */
303 u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */
304 u32 rtfrqcnt; /* PRGM=0: freq. count register */
306 u32 rsvd1[40];
312 u32 rdsta;
313 u32 rsvd2[15];
335 u32 rsvd1;
336 u32 mcr; /* MCFG Master Config Register */
337 u32 rsvd2;
338 u32 scfgr; /* SCFGR, Security Config Register */
343 u32 rsvd3[11];
344 u32 jrstart; /* JRSTART - Job Ring Start Register */
346 u32 rsvd4[5];
347 u32 deco_rsr; /* DECORSR - Deco Request Source */
348 u32 rsvd11;
349 u32 deco_rq; /* DECORR - DECO Request */
351 u32 rsvd5[22];
354 u32 deco_avail; /* DAR - DECO availability */
355 u32 deco_reset; /* DRR - DECO reset */
356 u32 rsvd6[182];
360 u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */
361 u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */
362 u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */
363 u32 rsvd7[32];
365 u32 rsvd8[70];
374 u32 rsvd9[448];
424 u32 rsvd1;
425 u32 inpring_size; /* IRSx - Input ring size */
426 u32 rsvd2;
427 u32 inpring_avail; /* IRSAx - Input ring room remaining */
428 u32 rsvd3;
429 u32 inpring_jobadd; /* IRJAx - Input ring jobs added */
433 u32 rsvd4;
434 u32 outring_size; /* ORSx - Output ring size */
435 u32 rsvd5;
436 u32 outring_rmvd; /* ORJRx - Output ring jobs removed */
437 u32 rsvd6;
438 u32 outring_used; /* ORSFx - Output ring slots full */
441 u32 rsvd7;
442 u32 jroutstatus; /* JRSTAx - JobR output status */
443 u32 rsvd8;
444 u32 jrintstatus; /* JRINTx - JobR interrupt status */
445 u32 rconfig_hi; /* JRxCFG - Ring configuration */
446 u32 rconfig_lo;
449 u32 rsvd9;
450 u32 inp_rdidx; /* IRRIx - Input ring read index */
451 u32 rsvd10;
452 u32 out_wtidx; /* ORWIx - Output ring write index */
455 u32 rsvd11;
456 u32 jrcommand; /* JRCRx - JobR command */
458 u32 rsvd12[932];
588 u32 rsvd;
589 u32 length;
597 u32 memhash_be[32];
598 u32 memhash_le[32];
603 u32 rsvd1;
604 u32 status; /* RSTA - Status */
605 u32 rsvd2;
606 u32 cmd; /* RCMD - Command */
607 u32 rsvd3;
608 u32 ctrl; /* RCTL - Control */
609 u32 rsvd4;
610 u32 throttle; /* RTHR - Throttle */
611 u32 rsvd5[2];
613 u32 rsvd6;
614 u32 rend; /* REND - Endian corrections */
615 u32 rsvd7[50];
619 u32 rsvd8[32];
623 u32 rsvd_3[640];
632 u32 qi_control_hi; /* QICTL - QI Control */
633 u32 qi_control_lo;
634 u32 rsvd1;
635 u32 qi_status; /* QISTA - QI Status */
636 u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */
637 u32 qi_deq_cfg_lo;
638 u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */
639 u32 qi_enq_cfg_lo;
640 u32 rsvd2[1016];
680 u32 elen; /* E, F bits + 30-bit length */
681 u32 bpid_offset; /* Buffer Pool ID + 16-bit length */
694 u32 rsvd1;
695 u32 cls1_mode; /* CxC1MR - Class 1 Mode */
696 u32 rsvd2;
697 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */
698 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */
699 u32 cls1_datasize_lo;
700 u32 rsvd3;
701 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */
702 u32 rsvd4[5];
703 u32 cha_ctrl; /* CCTLR - CHA control */
704 u32 rsvd5;
705 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */
706 u32 rsvd6;
707 u32 clr_written; /* CxCWR - Clear-Written */
708 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */
709 u32 ccb_status_lo;
710 u32 rsvd7[3];
711 u32 aad_size; /* CxAADSZR - Current AAD Size */
712 u32 rsvd8;
713 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */
714 u32 rsvd9[7];
715 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */
716 u32 rsvd10;
717 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */
718 u32 rsvd11;
719 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */
720 u32 rsvd12;
721 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */
722 u32 rsvd13[24];
723 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */
724 u32 rsvd14[48];
725 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */
726 u32 rsvd15[121];
727 u32 cls2_mode; /* CxC2MR - Class 2 Mode */
728 u32 rsvd16;
729 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */
730 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */
731 u32 cls2_datasize_lo;
732 u32 rsvd17;
733 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */
734 u32 rsvd18[56];
735 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */
736 u32 rsvd19[46];
737 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */
738 u32 rsvd20[84];
739 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */
740 u32 inp_infofifo_lo;
741 u32 rsvd21[2];
743 u32 rsvd22[2];
745 u32 rsvd23[2];
746 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */
747 u32 jr_ctl_lo;
750 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */
751 u32 op_status_lo;
752 u32 rsvd24[2];
753 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */
754 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */
755 u32 rsvd26[6];
757 u32 rsvd27[8];
759 u32 rsvd28[16];
761 u32 rsvd29[48];
762 u32 descbuf[64]; /* DxDESB - Descriptor buffer */
763 u32 rscvd30[193];
767 u32 desc_dbg; /* DxDDR - DECO Debug Register */
768 u32 rsvd31[126];