Lines Matching refs:cmd

267 	struct drv_cmd *cmd = _cmd;  in do_drv_read()  local
270 switch (cmd->type) { in do_drv_read()
273 rdmsr(cmd->addr.msr.reg, cmd->val, h); in do_drv_read()
276 acpi_os_read_port((acpi_io_address)cmd->addr.io.port, in do_drv_read()
277 &cmd->val, in do_drv_read()
278 (u32)cmd->addr.io.bit_width); in do_drv_read()
288 struct drv_cmd *cmd = _cmd; in do_drv_write() local
291 switch (cmd->type) { in do_drv_write()
293 rdmsr(cmd->addr.msr.reg, lo, hi); in do_drv_write()
294 lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE); in do_drv_write()
295 wrmsr(cmd->addr.msr.reg, lo, hi); in do_drv_write()
298 wrmsr(cmd->addr.msr.reg, cmd->val, 0); in do_drv_write()
301 acpi_os_write_port((acpi_io_address)cmd->addr.io.port, in do_drv_write()
302 cmd->val, in do_drv_write()
303 (u32)cmd->addr.io.bit_width); in do_drv_write()
310 static void drv_read(struct drv_cmd *cmd) in drv_read() argument
313 cmd->val = 0; in drv_read()
315 err = smp_call_function_any(cmd->mask, do_drv_read, cmd, 1); in drv_read()
319 static void drv_write(struct drv_cmd *cmd) in drv_write() argument
324 if (cpumask_test_cpu(this_cpu, cmd->mask)) in drv_write()
325 do_drv_write(cmd); in drv_write()
326 smp_call_function_many(cmd->mask, do_drv_write, cmd, 1); in drv_write()
333 struct drv_cmd cmd; in get_cur_val() local
340 cmd.type = SYSTEM_INTEL_MSR_CAPABLE; in get_cur_val()
341 cmd.addr.msr.reg = MSR_IA32_PERF_CTL; in get_cur_val()
344 cmd.type = SYSTEM_AMD_MSR_CAPABLE; in get_cur_val()
345 cmd.addr.msr.reg = MSR_AMD_PERF_CTL; in get_cur_val()
348 cmd.type = SYSTEM_IO_CAPABLE; in get_cur_val()
350 cmd.addr.io.port = perf->control_register.address; in get_cur_val()
351 cmd.addr.io.bit_width = perf->control_register.bit_width; in get_cur_val()
357 cmd.mask = mask; in get_cur_val()
358 drv_read(&cmd); in get_cur_val()
360 pr_debug("get_cur_val = %u\n", cmd.val); in get_cur_val()
362 return cmd.val; in get_cur_val()
413 struct drv_cmd cmd; in acpi_cpufreq_target() local
438 cmd.type = SYSTEM_INTEL_MSR_CAPABLE; in acpi_cpufreq_target()
439 cmd.addr.msr.reg = MSR_IA32_PERF_CTL; in acpi_cpufreq_target()
440 cmd.val = (u32) perf->states[next_perf_state].control; in acpi_cpufreq_target()
443 cmd.type = SYSTEM_AMD_MSR_CAPABLE; in acpi_cpufreq_target()
444 cmd.addr.msr.reg = MSR_AMD_PERF_CTL; in acpi_cpufreq_target()
445 cmd.val = (u32) perf->states[next_perf_state].control; in acpi_cpufreq_target()
448 cmd.type = SYSTEM_IO_CAPABLE; in acpi_cpufreq_target()
449 cmd.addr.io.port = perf->control_register.address; in acpi_cpufreq_target()
450 cmd.addr.io.bit_width = perf->control_register.bit_width; in acpi_cpufreq_target()
451 cmd.val = (u32) perf->states[next_perf_state].control; in acpi_cpufreq_target()
460 cmd.mask = policy->cpus; in acpi_cpufreq_target()
462 cmd.mask = cpumask_of(policy->cpu); in acpi_cpufreq_target()
464 drv_write(&cmd); in acpi_cpufreq_target()
467 if (!check_freqs(cmd.mask, data->freq_table[index].frequency, in acpi_cpufreq_target()