52 static unsigned long apbt_readl(struct dw_apb_timer *timer, unsigned long offs)  in apbt_readl()  argument
54 	return readl(timer->base + offs);  in apbt_readl()
57 static void apbt_writel(struct dw_apb_timer *timer, unsigned long val,  in apbt_writel()  argument
60 	writel(val, timer->base + offs);  in apbt_writel()
63 static void apbt_disable_int(struct dw_apb_timer *timer)  in apbt_disable_int()  argument
65 	unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL);  in apbt_disable_int()
68 	apbt_writel(timer, ctrl, APBTMR_N_CONTROL);  in apbt_disable_int()
78 	disable_irq(dw_ced->timer.irq);  in dw_apb_clockevent_pause()
79 	apbt_disable_int(&dw_ced->timer);  in dw_apb_clockevent_pause()
82 static void apbt_eoi(struct dw_apb_timer *timer)  in apbt_eoi()  argument
84 	apbt_readl(timer, APBTMR_N_EOI);  in apbt_eoi()
98 		dw_ced->eoi(&dw_ced->timer);  in dw_apb_clockevent_irq()
104 static void apbt_enable_int(struct dw_apb_timer *timer)  in apbt_enable_int()  argument
106 	unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL);  in apbt_enable_int()
108 	apbt_readl(timer, APBTMR_N_EOI);  in apbt_enable_int()
110 	apbt_writel(timer, ctrl, APBTMR_N_CONTROL);  in apbt_enable_int()
126 		period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);  in apbt_set_mode()
127 		ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);  in apbt_set_mode()
129 		apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);  in apbt_set_mode()
135 		apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);  in apbt_set_mode()
138 		apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT);  in apbt_set_mode()
140 		apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);  in apbt_set_mode()
144 		ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);  in apbt_set_mode()
153 		apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);  in apbt_set_mode()
155 		apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);  in apbt_set_mode()
161 		apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT);  in apbt_set_mode()
164 		apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);  in apbt_set_mode()
169 		ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);  in apbt_set_mode()
171 		apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);  in apbt_set_mode()
175 		apbt_enable_int(&dw_ced->timer);  in apbt_set_mode()
187 	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);  in apbt_next_event()
189 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);  in apbt_next_event()
191 	apbt_writel(&dw_ced->timer, delta, APBTMR_N_LOAD_COUNT);  in apbt_next_event()
193 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);  in apbt_next_event()
226 	dw_ced->timer.base = base;  in dw_apb_clockevent_init()
227 	dw_ced->timer.irq = irq;  in dw_apb_clockevent_init()
228 	dw_ced->timer.freq = freq;  in dw_apb_clockevent_init()
238 	dw_ced->ced.irq = dw_ced->timer.irq;  in dw_apb_clockevent_init()
267 	enable_irq(dw_ced->timer.irq);  in dw_apb_clockevent_resume()
277 	free_irq(dw_ced->timer.irq, &dw_ced->ced);  in dw_apb_clockevent_stop()
287 	apbt_writel(&dw_ced->timer, 0, APBTMR_N_CONTROL);  in dw_apb_clockevent_register()
289 	apbt_enable_int(&dw_ced->timer);  in dw_apb_clockevent_register()
306 	unsigned long ctrl = apbt_readl(&dw_cs->timer, APBTMR_N_CONTROL);  in dw_apb_clocksource_start()
309 	apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);  in dw_apb_clocksource_start()
310 	apbt_writel(&dw_cs->timer, ~0, APBTMR_N_LOAD_COUNT);  in dw_apb_clocksource_start()
314 	apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);  in dw_apb_clocksource_start()
325 	current_count = apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);  in __apbt_read_clocksource()
359 	dw_cs->timer.base = base;  in dw_apb_clocksource_init()
360 	dw_cs->timer.freq = freq;  in dw_apb_clocksource_init()
378 	clocksource_register_hz(&dw_cs->cs, dw_cs->timer.freq);  in dw_apb_clocksource_register()
388 	return (cycle_t)~apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);  in dw_apb_clocksource_read()