137 	clk = clk_register_mux(NULL, mux_name, parents, 4,  in zynq_clk_register_fclk()
141 	clk = clk_register_divider(NULL, div0_name, mux_name,  in zynq_clk_register_fclk()
145 	clk = clk_register_divider(NULL, div1_name, div0_name,  in zynq_clk_register_fclk()
150 	clks[fclk] = clk_register_gate(NULL, clk_name,  in zynq_clk_register_fclk()
195 	clk = clk_register_mux(NULL, mux_name, parents, 4,  in zynq_clk_register_periph_clk()
198 	clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,  in zynq_clk_register_periph_clk()
201 	clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,  in zynq_clk_register_periph_clk()
204 		clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,  in zynq_clk_register_periph_clk()
260 	ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT,  in zynq_clk_setup()
266 	clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],  in zynq_clk_setup()
272 	clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],  in zynq_clk_setup()
278 	clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],  in zynq_clk_setup()
284 	clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,  in zynq_clk_setup()
287 	clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,  in zynq_clk_setup()
291 	clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],  in zynq_clk_setup()
295 	clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,  in zynq_clk_setup()
297 	clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],  in zynq_clk_setup()
301 	clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,  in zynq_clk_setup()
303 	clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],  in zynq_clk_setup()
308 	clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,  in zynq_clk_setup()
310 	clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],  in zynq_clk_setup()
325 	clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],  in zynq_clk_setup()
331 	clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,  in zynq_clk_setup()
334 	clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],  in zynq_clk_setup()
337 	clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,  in zynq_clk_setup()
340 	clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],  in zynq_clk_setup()
344 	clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,  in zynq_clk_setup()
347 	clk = clk_register_divider(NULL, "dci_div1", "dci_div0",  in zynq_clk_setup()
351 	clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",  in zynq_clk_setup()
364 	zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,  in zynq_clk_setup()
367 	zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,  in zynq_clk_setup()
370 	zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,  in zynq_clk_setup()
392 	clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,  in zynq_clk_setup()
395 	clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,  in zynq_clk_setup()
398 	clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",  in zynq_clk_setup()
402 	clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,  in zynq_clk_setup()
406 	clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],  in zynq_clk_setup()
417 	clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,  in zynq_clk_setup()
420 	clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,  in zynq_clk_setup()
423 	clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",  in zynq_clk_setup()
427 	clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,  in zynq_clk_setup()
431 	clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],  in zynq_clk_setup()
449 	clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,  in zynq_clk_setup()
452 	clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,  in zynq_clk_setup()
455 	clk = clk_register_divider(NULL, "can_div1", "can_div0",  in zynq_clk_setup()
459 	clk = clk_register_gate(NULL, "can0_gate", "can_div1",  in zynq_clk_setup()
462 	clk = clk_register_gate(NULL, "can1_gate", "can_div1",  in zynq_clk_setup()
465 	clk = clk_register_mux(NULL, "can0_mio_mux",  in zynq_clk_setup()
469 	clk = clk_register_mux(NULL, "can1_mio_mux",  in zynq_clk_setup()
473 	clks[can0] = clk_register_mux(NULL, clk_output_name[can0],  in zynq_clk_setup()
477 	clks[can1] = clk_register_mux(NULL, clk_output_name[can1],  in zynq_clk_setup()
489 	clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,  in zynq_clk_setup()
492 	clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,  in zynq_clk_setup()
495 	clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,  in zynq_clk_setup()
498 	clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],  in zynq_clk_setup()
501 	clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],  in zynq_clk_setup()
515 	clks[dma] = clk_register_gate(NULL, clk_output_name[dma],  in zynq_clk_setup()
518 	clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],  in zynq_clk_setup()
521 	clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],  in zynq_clk_setup()
524 	clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],  in zynq_clk_setup()
527 	clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],  in zynq_clk_setup()
530 	clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],  in zynq_clk_setup()
533 	clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],  in zynq_clk_setup()
536 	clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],  in zynq_clk_setup()
539 	clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],  in zynq_clk_setup()
542 	clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],  in zynq_clk_setup()
545 	clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],  in zynq_clk_setup()
548 	clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],  in zynq_clk_setup()
551 	clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],  in zynq_clk_setup()
554 	clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],  in zynq_clk_setup()
557 	clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],  in zynq_clk_setup()
560 	clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],  in zynq_clk_setup()
563 	clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],  in zynq_clk_setup()
566 	clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],  in zynq_clk_setup()
591 	np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc");  in zynq_clock_init()