Lines Matching refs:CLK_DIVIDER_ONE_BASED
142 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_register_fclk()
147 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_register_fclk()
199 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); in zynq_clk_register_periph_clk()
288 SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
332 SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
338 SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
345 SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
349 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
396 SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
400 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
421 SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
425 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
453 SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
457 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
493 SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()