Lines Matching refs:CLK_DIVIDER_ALLOW_ZERO
143 CLK_DIVIDER_ALLOW_ZERO, fclk_lock); in zynq_clk_register_fclk()
147 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_register_fclk()
199 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); in zynq_clk_register_periph_clk()
289 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); in zynq_clk_setup()
333 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); in zynq_clk_setup()
339 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); in zynq_clk_setup()
346 CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); in zynq_clk_setup()
349 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
397 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); in zynq_clk_setup()
400 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
422 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); in zynq_clk_setup()
425 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
454 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); in zynq_clk_setup()
457 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
494 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); in zynq_clk_setup()