82 				CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8540_clk_init()
91 				CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8540_clk_init()
94 				CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8540_clk_init()
97 				CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8540_clk_init()
133 				CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8540_clk_init()
152 					CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8540_clk_init()
157 					CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8540_clk_init()
167 				CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8540_clk_init()
171 				PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
176 				PRCMU_PLLDSI_LCD, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
180 				PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
184 				PRCMU_DSI0CLK_LCD, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
189 				PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
193 				PRCMU_DSI1CLK_LCD, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
198 				PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
203 				PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
208 				PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
445 			clkrst1_base, BIT(0), CLK_SET_RATE_GATE);  in u8540_clk_init()
449 			clkrst1_base, BIT(1), CLK_SET_RATE_GATE);  in u8540_clk_init()
453 			clkrst1_base, BIT(2), CLK_SET_RATE_GATE);  in u8540_clk_init()
457 			clkrst1_base, BIT(3), CLK_SET_RATE_GATE);  in u8540_clk_init()
462 			clkrst1_base, BIT(4), CLK_SET_RATE_GATE);  in u8540_clk_init()
467 			clkrst1_base, BIT(5), CLK_SET_RATE_GATE);  in u8540_clk_init()
471 			clkrst1_base, BIT(6), CLK_SET_RATE_GATE);  in u8540_clk_init()
475 			clkrst1_base, BIT(8), CLK_SET_RATE_GATE);  in u8540_clk_init()
479 			clkrst1_base, BIT(9), CLK_SET_RATE_GATE);  in u8540_clk_init()
483 			clkrst1_base, BIT(10), CLK_SET_RATE_GATE);  in u8540_clk_init()
489 			clkrst2_base, BIT(0), CLK_SET_RATE_GATE);  in u8540_clk_init()
493 			clkrst2_base, BIT(1), CLK_SET_RATE_GATE);  in u8540_clk_init()
497 			clkrst2_base, BIT(2), CLK_SET_RATE_GATE);  in u8540_clk_init()
501 			clkrst2_base, BIT(3), CLK_SET_RATE_GATE);  in u8540_clk_init()
506 			clkrst2_base, BIT(4), CLK_SET_RATE_GATE);  in u8540_clk_init()
510 			clkrst2_base, BIT(5), CLK_SET_RATE_GATE);  in u8540_clk_init()
515 			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);  in u8540_clk_init()
520 			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);  in u8540_clk_init()
525 			clkrst2_base, BIT(9), CLK_SET_RATE_GATE);  in u8540_clk_init()
531 			clkrst3_base, BIT(1), CLK_SET_RATE_GATE);  in u8540_clk_init()
535 			clkrst3_base, BIT(2), CLK_SET_RATE_GATE);  in u8540_clk_init()
539 			clkrst3_base, BIT(3), CLK_SET_RATE_GATE);  in u8540_clk_init()
543 			clkrst3_base, BIT(4), CLK_SET_RATE_GATE);  in u8540_clk_init()
547 			clkrst3_base, BIT(5), CLK_SET_RATE_GATE);  in u8540_clk_init()
552 			clkrst3_base, BIT(6), CLK_SET_RATE_GATE);  in u8540_clk_init()
556 			clkrst3_base, BIT(7), CLK_SET_RATE_GATE);  in u8540_clk_init()
560 			clkrst3_base, BIT(8), CLK_SET_RATE_GATE);  in u8540_clk_init()
564 			clkrst3_base, BIT(9), CLK_SET_RATE_GATE);  in u8540_clk_init()
568 			clkrst3_base, BIT(10), CLK_SET_RATE_GATE);  in u8540_clk_init()
572 			clkrst3_base, BIT(11), CLK_SET_RATE_GATE);  in u8540_clk_init()
577 			clkrst6_base, BIT(0), CLK_SET_RATE_GATE);  in u8540_clk_init()