Lines Matching refs:mux

33 	struct clk_mux *mux = to_clk_mux(hw);  in ti_clk_mux_get_parent()  local
44 val = ti_clk_ll_ops->clk_readl(mux->reg) >> mux->shift; in ti_clk_mux_get_parent()
45 val &= mux->mask; in ti_clk_mux_get_parent()
47 if (mux->table) { in ti_clk_mux_get_parent()
51 if (mux->table[i] == val) in ti_clk_mux_get_parent()
56 if (val && (mux->flags & CLK_MUX_INDEX_BIT)) in ti_clk_mux_get_parent()
59 if (val && (mux->flags & CLK_MUX_INDEX_ONE)) in ti_clk_mux_get_parent()
70 struct clk_mux *mux = to_clk_mux(hw); in ti_clk_mux_set_parent() local
74 if (mux->table) { in ti_clk_mux_set_parent()
75 index = mux->table[index]; in ti_clk_mux_set_parent()
77 if (mux->flags & CLK_MUX_INDEX_BIT) in ti_clk_mux_set_parent()
80 if (mux->flags & CLK_MUX_INDEX_ONE) in ti_clk_mux_set_parent()
84 if (mux->lock) in ti_clk_mux_set_parent()
85 spin_lock_irqsave(mux->lock, flags); in ti_clk_mux_set_parent()
87 if (mux->flags & CLK_MUX_HIWORD_MASK) { in ti_clk_mux_set_parent()
88 val = mux->mask << (mux->shift + 16); in ti_clk_mux_set_parent()
90 val = ti_clk_ll_ops->clk_readl(mux->reg); in ti_clk_mux_set_parent()
91 val &= ~(mux->mask << mux->shift); in ti_clk_mux_set_parent()
93 val |= index << mux->shift; in ti_clk_mux_set_parent()
94 ti_clk_ll_ops->clk_writel(val, mux->reg); in ti_clk_mux_set_parent()
96 if (mux->lock) in ti_clk_mux_set_parent()
97 spin_unlock_irqrestore(mux->lock, flags); in ti_clk_mux_set_parent()
114 struct clk_mux *mux; in _register_mux() local
119 mux = kzalloc(sizeof(*mux), GFP_KERNEL); in _register_mux()
120 if (!mux) { in _register_mux()
132 mux->reg = reg; in _register_mux()
133 mux->shift = shift; in _register_mux()
134 mux->mask = mask; in _register_mux()
135 mux->flags = clk_mux_flags; in _register_mux()
136 mux->lock = lock; in _register_mux()
137 mux->table = table; in _register_mux()
138 mux->hw.init = &init; in _register_mux()
140 clk = clk_register(dev, &mux->hw); in _register_mux()
143 kfree(mux); in _register_mux()
150 struct ti_clk_mux *mux; in ti_clk_register_mux() local
159 mux = setup->data; in ti_clk_register_mux()
162 mask = mux->num_parents; in ti_clk_register_mux()
163 if (!(mux->flags & CLKF_INDEX_STARTS_AT_ONE)) in ti_clk_register_mux()
167 reg_setup->index = mux->module; in ti_clk_register_mux()
168 reg_setup->offset = mux->reg; in ti_clk_register_mux()
170 if (mux->flags & CLKF_INDEX_STARTS_AT_ONE) in ti_clk_register_mux()
173 if (mux->flags & CLKF_SET_RATE_PARENT) in ti_clk_register_mux()
176 return _register_mux(NULL, setup->name, mux->parents, mux->num_parents, in ti_clk_register_mux()
177 flags, (void __iomem *)reg, mux->bit_shift, mask, in ti_clk_register_mux()
245 struct clk_mux *mux; in ti_clk_build_component_mux() local
252 mux = kzalloc(sizeof(*mux), GFP_KERNEL); in ti_clk_build_component_mux()
253 if (!mux) in ti_clk_build_component_mux()
256 reg = (struct clk_omap_reg *)&mux->reg; in ti_clk_build_component_mux()
258 mux->shift = setup->bit_shift; in ti_clk_build_component_mux()
264 mux->flags |= CLK_MUX_INDEX_ONE; in ti_clk_build_component_mux()
268 mux->mask = num_parents - 1; in ti_clk_build_component_mux()
269 mux->mask = (1 << fls(mux->mask)) - 1; in ti_clk_build_component_mux()
271 return &mux->hw; in ti_clk_build_component_mux()
276 struct clk_mux *mux; in of_ti_composite_mux_clk_setup() local
280 mux = kzalloc(sizeof(*mux), GFP_KERNEL); in of_ti_composite_mux_clk_setup()
281 if (!mux) in of_ti_composite_mux_clk_setup()
284 mux->reg = ti_clk_get_reg_addr(node, 0); in of_ti_composite_mux_clk_setup()
286 if (IS_ERR(mux->reg)) in of_ti_composite_mux_clk_setup()
290 mux->shift = val; in of_ti_composite_mux_clk_setup()
293 mux->flags |= CLK_MUX_INDEX_ONE; in of_ti_composite_mux_clk_setup()
302 mux->mask = num_parents - 1; in of_ti_composite_mux_clk_setup()
303 mux->mask = (1 << fls(mux->mask)) - 1; in of_ti_composite_mux_clk_setup()
305 if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX)) in of_ti_composite_mux_clk_setup()
309 kfree(mux); in of_ti_composite_mux_clk_setup()