Lines Matching refs:NULL
23 DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
24 DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
25 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
26 DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
27 DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
28 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
29 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
30 DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
31 DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
32 DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
33 DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
34 DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
35 DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
36 DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
37 DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
38 DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
39 DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
40 DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"),
41 DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
42 DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
43 DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
44 DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
45 DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
46 DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
47 DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
48 DT_CLK(NULL, "cefuse_fck", "cefuse_fck"),
49 DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
50 DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
51 DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
52 DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
53 DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
54 DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
55 DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
56 DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
57 DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
58 DT_CLK(NULL, "mmu_fck", "mmu_fck"),
59 DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
60 DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
61 DT_CLK(NULL, "sha0_fck", "sha0_fck"),
62 DT_CLK(NULL, "aes0_fck", "aes0_fck"),
63 DT_CLK(NULL, "rng_fck", "rng_fck"),
64 DT_CLK(NULL, "timer1_fck", "timer1_fck"),
65 DT_CLK(NULL, "timer2_fck", "timer2_fck"),
66 DT_CLK(NULL, "timer3_fck", "timer3_fck"),
67 DT_CLK(NULL, "timer4_fck", "timer4_fck"),
68 DT_CLK(NULL, "timer5_fck", "timer5_fck"),
69 DT_CLK(NULL, "timer6_fck", "timer6_fck"),
70 DT_CLK(NULL, "timer7_fck", "timer7_fck"),
71 DT_CLK(NULL, "usbotg_fck", "usbotg_fck"),
72 DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"),
73 DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
74 DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"),
75 DT_CLK(NULL, "l3_gclk", "l3_gclk"),
76 DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
77 DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
78 DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
79 DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"),
80 DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
81 DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
82 DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"),
83 DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
84 DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
85 DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
86 DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
87 DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
88 DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
89 DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
90 DT_CLK(NULL, "lcd_gclk", "lcd_gclk"),
91 DT_CLK(NULL, "mmc_clk", "mmc_clk"),
92 DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
93 DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
94 DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"),
95 DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"),
96 DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
97 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
98 DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"),
99 DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"),
100 DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"),
101 DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"),
102 DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
103 DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
104 DT_CLK(NULL, "clkout2_ck", "clkout2_ck"),
108 { .node_name = NULL },
142 clk1 = clk_get_sys(NULL, "sys_clkin_ck"); in am33xx_dt_clk_init()
143 clk2 = clk_get_sys(NULL, "timer3_fck"); in am33xx_dt_clk_init()
146 clk2 = clk_get_sys(NULL, "timer6_fck"); in am33xx_dt_clk_init()
155 clk1 = clk_get_sys(NULL, "wdt1_fck"); in am33xx_dt_clk_init()
156 clk2 = clk_get_sys(NULL, "clkdiv32k_ick"); in am33xx_dt_clk_init()