132 			    _clk_num, _gate_flags, _clk_id)	\  argument
135 			_clk_num,  _gate_flags, _clk_id, _parents##_idx, 0,\
139 			    _clk_num, _gate_flags, _clk_id, flags)\  argument
142 			_clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
146 			     _clk_num, _gate_flags, _clk_id)	\  argument
149 			_clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
152 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock)	\  argument
155 			      0, TEGRA_PERIPH_NO_GATE, _clk_id,\
159 			    _clk_num, _gate_flags, _clk_id)	\  argument
163 			_clk_id, _parents##_idx, 0, NULL)
166 			    _clk_num, _gate_flags, _clk_id, flags)\  argument
170 			_clk_id, _parents##_idx, flags, NULL)
173 			    _clk_num, _gate_flags, _clk_id)	\  argument
177 			_clk_id, _parents##_idx, 0, NULL)
180 			     _clk_num, _clk_id)			\  argument
183 			TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
187 			     _clk_num, _clk_id)			\  argument
190 			_clk_num, 0, _clk_id, _parents##_idx, 0, NULL)
193 			     _clk_num, _gate_flags, _clk_id)	 \  argument
197 			_clk_id, _parents##_idx, 0, NULL)
200 				 _gate_flags, _clk_id)		\  argument
204 			_clk_id, mux_d_audio_clk_idx, 0, NULL)
208 			      _gate_flags, _clk_id, _lock)		\  argument
212 			_clk_id, _parents##_idx, 0, _lock)
215 			     _clk_num, _gate_flags,  _clk_id, _flags)	\  argument
218 		.clk_id = _clk_id,					\