45 	struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);  in clk_super_get_parent()  local
49 	val = readl_relaxed(mux->reg);  in clk_super_get_parent()
56 		super_state_to_src_shift(mux, SUPER_STATE_IDLE) :  in clk_super_get_parent()
57 		super_state_to_src_shift(mux, SUPER_STATE_RUN);  in clk_super_get_parent()
59 	source = (val >> shift) & super_state_to_src_mask(mux);  in clk_super_get_parent()
65 	if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) &&  in clk_super_get_parent()
66 	    (source == mux->pllx_index))  in clk_super_get_parent()
67 		source = mux->div2_index;  in clk_super_get_parent()
74 	struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);  in clk_super_set_parent()  local
80 	if (mux->lock)  in clk_super_set_parent()
81 		spin_lock_irqsave(mux->lock, flags);  in clk_super_set_parent()
83 	val = readl_relaxed(mux->reg);  in clk_super_set_parent()
88 		super_state_to_src_shift(mux, SUPER_STATE_IDLE) :  in clk_super_set_parent()
89 		super_state_to_src_shift(mux, SUPER_STATE_RUN);  in clk_super_set_parent()
96 	if ((mux->flags & TEGRA_DIVIDER_2) && ((index == mux->div2_index) ||  in clk_super_set_parent()
97 					       (index == mux->pllx_index))) {  in clk_super_set_parent()
99 		if ((parent_index == mux->div2_index) ||  in clk_super_set_parent()
100 		    (parent_index == mux->pllx_index)) {  in clk_super_set_parent()
106 		writel_relaxed(val, mux->reg);  in clk_super_set_parent()
109 		if (index == mux->div2_index)  in clk_super_set_parent()
110 			index = mux->pllx_index;  in clk_super_set_parent()
112 	val &= ~((super_state_to_src_mask(mux)) << shift);  in clk_super_set_parent()
113 	val |= (index & (super_state_to_src_mask(mux))) << shift;  in clk_super_set_parent()
115 	writel_relaxed(val, mux->reg);  in clk_super_set_parent()
119 	if (mux->lock)  in clk_super_set_parent()
120 		spin_unlock_irqrestore(mux->lock, flags);  in clk_super_set_parent()