191 	struct mmc_phase *phase = to_mmc_phase(hw);  in mmc_get_phase()  local
197 	value = readl(phase->reg);  in mmc_get_phase()
198 	delay = (value >> phase->offset) & 0x3;  in mmc_get_phase()
233 	struct mmc_phase *phase = to_mmc_phase(hw);  in mmc_set_phase()  local
284 	spin_lock_irqsave(phase->lock, flags);  in mmc_set_phase()
285 	value = readl(phase->reg);  in mmc_set_phase()
286 	value &= ~GENMASK(phase->offset + 3, phase->offset);  in mmc_set_phase()
287 	value |= delay << phase->offset;  in mmc_set_phase()
288 	writel(value, phase->reg);  in mmc_set_phase()
289 	spin_unlock_irqrestore(phase->lock, flags);  in mmc_set_phase()
342 		struct mmc_phase *phase;  in sunxi_mmc_setup()  local
344 		phase = kmalloc(sizeof(*phase), GFP_KERNEL);  in sunxi_mmc_setup()
345 		if (!phase)  in sunxi_mmc_setup()
348 		phase->hw.init = &init;  in sunxi_mmc_setup()
349 		phase->reg = reg;  in sunxi_mmc_setup()
350 		phase->lock = lock;  in sunxi_mmc_setup()
353 			phase->offset = 8;  in sunxi_mmc_setup()
355 			phase->offset = 20;  in sunxi_mmc_setup()
361 		clk_data->clks[i] = clk_register(NULL, &phase->hw);  in sunxi_mmc_setup()
363 			kfree(phase);  in sunxi_mmc_setup()