77 sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,  in sh73a0_cpg_register_clock()  argument
88 		u32 parent_idx = (clk_readl(cpg->reg + CPG_CKSCR) >> 28) & 3;  in sh73a0_cpg_register_clock()
93 		void __iomem *enable_reg = cpg->reg;  in sh73a0_cpg_register_clock()
113 		if (clk_readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {  in sh73a0_cpg_register_clock()
122 		void __iomem *dsi_reg = cpg->reg +  in sh73a0_cpg_register_clock()
159 						  cpg->reg + reg, shift, width, 0,  in sh73a0_cpg_register_clock()
160 						  table, &cpg->lock);  in sh73a0_cpg_register_clock()
166 	struct sh73a0_cpg *cpg;  in sh73a0_cpg_clocks_init()  local
177 	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);  in sh73a0_cpg_clocks_init()
179 	if (cpg == NULL || clks == NULL) {  in sh73a0_cpg_clocks_init()
186 	spin_lock_init(&cpg->lock);  in sh73a0_cpg_clocks_init()
188 	cpg->data.clks = clks;  in sh73a0_cpg_clocks_init()
189 	cpg->data.clk_num = num_clks;  in sh73a0_cpg_clocks_init()
191 	cpg->reg = of_iomap(np, 0);  in sh73a0_cpg_clocks_init()
192 	if (WARN_ON(cpg->reg == NULL))  in sh73a0_cpg_clocks_init()
196 	clk_writel(0x108, cpg->reg + CPG_SD0CKCR);  in sh73a0_cpg_clocks_init()
197 	clk_writel(0x108, cpg->reg + CPG_SD1CKCR);  in sh73a0_cpg_clocks_init()
198 	clk_writel(0x108, cpg->reg + CPG_SD2CKCR);  in sh73a0_cpg_clocks_init()
207 		clk = sh73a0_cpg_register_clock(np, cpg, name);  in sh73a0_cpg_clocks_init()
212 			cpg->data.clks[i] = clk;  in sh73a0_cpg_clocks_init()
215 	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);  in sh73a0_cpg_clocks_init()