Lines Matching refs:GATE
147 GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
149 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
151 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
153 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
156 GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
157 GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
158 GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
160 GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
161 GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
162 GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
164 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
166 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
168 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",