Lines Matching refs:GATE
433 GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
435 GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
437 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
439 GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
443 GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
445 GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
447 GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
449 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
451 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
453 GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
457 GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
459 GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
461 GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
463 GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
465 GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
467 GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
469 GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
470 GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
471 GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
472 GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
473 GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
475 GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
477 GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
479 GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
481 GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
483 GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
485 GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
487 GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
489 GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
491 GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
493 GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
495 GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
499 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk",
501 GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk",
503 GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk",
505 GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk",
509 GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
513 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
517 GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0",
519 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
521 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
525 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
527 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
529 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp",
531 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp",
535 GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),
536 GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
538 GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
540 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
542 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
546 GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
548 GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
550 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
552 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
554 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
556 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
560 GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19,
562 GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320",
564 GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",
566 GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320",
568 GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320",
570 GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320",
572 GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320",
574 GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320",
576 GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320",
578 GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320",
580 GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320",
582 GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0),
583 GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320",
585 GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),
586 GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0),
589 GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,
591 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
593 GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
594 GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
597 GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0),
598 GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,
600 GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
602 GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
605 GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7,
607 GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6,
609 GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
611 GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
612 GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
613 GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
614 GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
617 GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
618 GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub",
620 GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub",
622 GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub",
626 GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
627 GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
629 GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
630 GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
631 GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
632 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
633 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
634 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
635 GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
638 GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
639 GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
640 GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0),
641 GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
642 GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
643 GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
644 GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
645 GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
646 GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
647 GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
648 GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
649 GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
650 GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
651 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
652 GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
939 GATE(CLK_UART_ISP, "uart_isp", "uart_isp_top",
941 GATE(CLK_WDT_ISP, "wdt_isp", "mout_aclk_266_sub",
943 GATE(CLK_PWM_ISP, "pwm_isp", "mout_aclk_266_sub",
945 GATE(CLK_I2C1_ISP, "i2c1_isp", "mout_aclk_266_sub",
947 GATE(CLK_I2C0_ISP, "i2c0_isp", "mout_aclk_266_sub",
949 GATE(CLK_MPWM_ISP, "mpwm_isp", "mout_aclk_266_sub",
951 GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "mout_aclk_266_sub",
953 GATE(CLK_PPMUISPX, "ppmuispx", "mout_aclk_266_sub",
955 GATE(CLK_PPMUISPMX, "ppmuispmx", "mout_aclk_266_sub",
957 GATE(CLK_QE_LITE1, "qe_lite1", "mout_aclk_266_sub",
959 GATE(CLK_QE_LITE0, "qe_lite0", "mout_aclk_266_sub",
961 GATE(CLK_QE_FD, "qe_fd", "mout_aclk_266_sub",
963 GATE(CLK_QE_DRC, "qe_drc", "mout_aclk_266_sub",
965 GATE(CLK_QE_ISP, "qe_isp", "mout_aclk_266_sub",
967 GATE(CLK_CSIS1, "csis1", "mout_aclk_266_sub",
969 GATE(CLK_SMMU_LITE1, "smmu_lite1", "mout_aclk_266_sub",
971 GATE(CLK_SMMU_LITE0, "smmu_lite0", "mout_aclk_266_sub",
973 GATE(CLK_SMMU_FD, "smmu_fd", "mout_aclk_266_sub",
975 GATE(CLK_SMMU_DRC, "smmu_drc", "mout_aclk_266_sub",
977 GATE(CLK_SMMU_ISP, "smmu_isp", "mout_aclk_266_sub",
979 GATE(CLK_GICISP, "gicisp", "mout_aclk_266_sub",
981 GATE(CLK_CSIS0, "csis0", "mout_aclk_266_sub",
983 GATE(CLK_MCUISP, "mcuisp", "mout_aclk_266_sub",
985 GATE(CLK_LITE1, "lite1", "mout_aclk_266_sub",
987 GATE(CLK_LITE0, "lite0", "mout_aclk_266_sub",
989 GATE(CLK_FD, "fd", "mout_aclk_266_sub",
991 GATE(CLK_DRC, "drc", "mout_aclk_266_sub",
993 GATE(CLK_ISP, "isp", "mout_aclk_266_sub",
997 GATE(CLK_QE_ISPCX, "qe_ispcx", "uart_isp_top",
999 GATE(CLK_QE_SCALERP, "qe_scalerp", "uart_isp_top",
1001 GATE(CLK_QE_SCALERC, "qe_scalerc", "uart_isp_top",
1003 GATE(CLK_SMMU_SCALERP, "smmu_scalerp", "uart_isp_top",
1005 GATE(CLK_SMMU_SCALERC, "smmu_scalerc", "uart_isp_top",
1007 GATE(CLK_SCALERP, "scalerp", "uart_isp_top",
1009 GATE(CLK_SCALERC, "scalerc", "uart_isp_top",
1011 GATE(CLK_SPI1_ISP, "spi1_isp", "uart_isp_top",
1013 GATE(CLK_SPI0_ISP, "spi0_isp", "uart_isp_top",
1015 GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "uart_isp_top",
1017 GATE(CLK_ASYNCAXIM, "asyncaxim", "uart_isp_top",
1021 GATE(CLK_SCLK_MPWM_ISP, "sclk_mpwm_isp", "div_mpwm",