Lines Matching refs:pll_mux
33 struct clk_mux pll_mux; member
165 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3066_pll_set_rate() local
191 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3066_pll_set_rate()
193 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3066_pll_set_rate()
229 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3066_pll_set_rate()
341 struct clk_mux *pll_mux; in rockchip_clk_register_pll() local
404 pll_mux = &pll->pll_mux; in rockchip_clk_register_pll()
405 pll_mux->reg = base + mode_offset; in rockchip_clk_register_pll()
406 pll_mux->shift = mode_shift; in rockchip_clk_register_pll()
407 pll_mux->mask = PLL_MODE_MASK; in rockchip_clk_register_pll()
408 pll_mux->flags = 0; in rockchip_clk_register_pll()
409 pll_mux->lock = lock; in rockchip_clk_register_pll()
410 pll_mux->hw.init = &init; in rockchip_clk_register_pll()
413 pll_mux->flags |= CLK_MUX_HIWORD_MASK; in rockchip_clk_register_pll()
434 mux_clk = clk_register(NULL, &pll_mux->hw); in rockchip_clk_register_pll()