52 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_is_enabled()  local
56 	ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);  in clk_rcg2_is_enabled()
65 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_get_parent()  local
70 	ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_rcg2_get_parent()
78 		if (cfg == rcg->parent_map[i].cfg)  in clk_rcg2_get_parent()
87 static int update_config(struct clk_rcg2 *rcg)  in update_config()  argument
91 	struct clk_hw *hw = &rcg->clkr.hw;  in update_config()
94 	ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,  in update_config()
101 		ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);  in update_config()
115 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_set_parent()  local
117 	u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;  in clk_rcg2_set_parent()
119 	ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in clk_rcg2_set_parent()
124 	return update_config(rcg);  in clk_rcg2_set_parent()
155 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_recalc_rate()  local
158 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_rcg2_recalc_rate()
160 	if (rcg->mnd_width) {  in clk_rcg2_recalc_rate()
161 		mask = BIT(rcg->mnd_width) - 1;  in clk_rcg2_recalc_rate()
162 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m);  in clk_rcg2_recalc_rate()
164 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n);  in clk_rcg2_recalc_rate()
172 	mask = BIT(rcg->hid_width) - 1;  in clk_rcg2_recalc_rate()
185 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in _freq_tbl_determine_rate()  local
192 	index = qcom_find_src_index(hw, rcg->parent_map, f->src);  in _freq_tbl_determine_rate()
223 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_determine_rate()  local
225 	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);  in clk_rcg2_determine_rate()
228 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)  in clk_rcg2_configure()  argument
231 	struct clk_hw *hw = &rcg->clkr.hw;  in clk_rcg2_configure()
232 	int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);  in clk_rcg2_configure()
237 	if (rcg->mnd_width && f->n) {  in clk_rcg2_configure()
238 		mask = BIT(rcg->mnd_width) - 1;  in clk_rcg2_configure()
239 		ret = regmap_update_bits(rcg->clkr.regmap,  in clk_rcg2_configure()
240 				rcg->cmd_rcgr + M_REG, mask, f->m);  in clk_rcg2_configure()
244 		ret = regmap_update_bits(rcg->clkr.regmap,  in clk_rcg2_configure()
245 				rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));  in clk_rcg2_configure()
249 		ret = regmap_update_bits(rcg->clkr.regmap,  in clk_rcg2_configure()
250 				rcg->cmd_rcgr + D_REG, mask, ~f->n);  in clk_rcg2_configure()
255 	mask = BIT(rcg->hid_width) - 1;  in clk_rcg2_configure()
258 	cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;  in clk_rcg2_configure()
259 	if (rcg->mnd_width && f->n && (f->m != f->n))  in clk_rcg2_configure()
261 	ret = regmap_update_bits(rcg->clkr.regmap,  in clk_rcg2_configure()
262 			rcg->cmd_rcgr + CFG_REG, mask, cfg);  in clk_rcg2_configure()
266 	return update_config(rcg);  in clk_rcg2_configure()
271 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in __clk_rcg2_set_rate()  local
274 	f = qcom_find_freq(rcg->freq_tbl, rate);  in __clk_rcg2_set_rate()
278 	return clk_rcg2_configure(rcg, f);  in __clk_rcg2_set_rate()
334 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_edp_pixel_set_rate()  local
335 	struct freq_tbl f = *rcg->freq_tbl;  in clk_edp_pixel_set_rate()
340 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_edp_pixel_set_rate()
356 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in clk_edp_pixel_set_rate()
364 		return clk_rcg2_configure(rcg, &f);  in clk_edp_pixel_set_rate()
382 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_edp_pixel_determine_rate()  local
383 	const struct freq_tbl *f = rcg->freq_tbl;  in clk_edp_pixel_determine_rate()
388 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_edp_pixel_determine_rate()
390 	int index = qcom_find_src_index(hw, rcg->parent_map, f->src);  in clk_edp_pixel_determine_rate()
408 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in clk_edp_pixel_determine_rate()
435 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_byte_determine_rate()  local
436 	const struct freq_tbl *f = rcg->freq_tbl;  in clk_byte_determine_rate()
437 	int index = qcom_find_src_index(hw, rcg->parent_map, f->src);  in clk_byte_determine_rate()
439 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_byte_determine_rate()
458 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_byte_set_rate()  local
459 	struct freq_tbl f = *rcg->freq_tbl;  in clk_byte_set_rate()
461 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_byte_set_rate()
468 	return clk_rcg2_configure(rcg, &f);  in clk_byte_set_rate()
502 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_pixel_determine_rate()  local
505 	const struct freq_tbl *f = rcg->freq_tbl;  in clk_pixel_determine_rate()
507 	int index = qcom_find_src_index(hw, rcg->parent_map, f->src);  in clk_pixel_determine_rate()
530 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_pixel_set_rate()  local
531 	struct freq_tbl f = *rcg->freq_tbl;  in clk_pixel_set_rate()
535 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_pixel_set_rate()
545 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in clk_pixel_set_rate()
553 		return clk_rcg2_configure(rcg, &f);  in clk_pixel_set_rate()