47 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_get_parent()  local
52 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_get_parent()
55 	ns = ns_to_src(&rcg->s, ns);  in clk_rcg_get_parent()
57 		if (ns == rcg->s.parent_map[i].cfg)  in clk_rcg_get_parent()
66 static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)  in reg_to_bank()  argument
68 	bank &= BIT(rcg->mux_sel_bit);  in reg_to_bank()
74 	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);  in clk_dyn_rcg_get_parent()  local
81 	ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in clk_dyn_rcg_get_parent()
84 	bank = reg_to_bank(rcg, reg);  in clk_dyn_rcg_get_parent()
85 	s = &rcg->s[bank];  in clk_dyn_rcg_get_parent()
87 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);  in clk_dyn_rcg_get_parent()
104 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_set_parent()  local
107 	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_set_parent()
108 	ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns);  in clk_rcg_set_parent()
109 	regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);  in clk_rcg_set_parent()
206 static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)  in configure_bank()  argument
215 	bool banked_mn = !!rcg->mn[1].width;  in configure_bank()
216 	bool banked_p = !!rcg->p[1].pre_div_width;  in configure_bank()
217 	struct clk_hw *hw = &rcg->clkr.hw;  in configure_bank()
221 	ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in configure_bank()
224 	bank = reg_to_bank(rcg, reg);  in configure_bank()
227 	ns_reg = rcg->ns_reg[new_bank];  in configure_bank()
228 	ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns);  in configure_bank()
233 		mn = &rcg->mn[new_bank];  in configure_bank()
234 		md_reg = rcg->md_reg[new_bank];  in configure_bank()
237 		ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
241 		ret = regmap_read(rcg->clkr.regmap, md_reg, &md);  in configure_bank()
245 		ret = regmap_write(rcg->clkr.regmap, md_reg, md);  in configure_bank()
249 		ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
254 		if (rcg->ns_reg[0] != rcg->ns_reg[1]) {  in configure_bank()
256 			ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
261 			ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg,  in configure_bank()
268 		ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
274 		p = &rcg->p[new_bank];  in configure_bank()
278 	s = &rcg->s[new_bank];  in configure_bank()
283 	ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
288 		ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in configure_bank()
291 		reg ^= BIT(rcg->mux_sel_bit);  in configure_bank()
292 		ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);  in configure_bank()
301 	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);  in clk_dyn_rcg_set_parent()  local
305 	bool banked_mn = !!rcg->mn[1].width;  in clk_dyn_rcg_set_parent()
306 	bool banked_p = !!rcg->p[1].pre_div_width;  in clk_dyn_rcg_set_parent()
308 	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in clk_dyn_rcg_set_parent()
309 	bank = reg_to_bank(rcg, reg);  in clk_dyn_rcg_set_parent()
311 	regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);  in clk_dyn_rcg_set_parent()
314 		regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);  in clk_dyn_rcg_set_parent()
315 		f.m = md_to_m(&rcg->mn[bank], md);  in clk_dyn_rcg_set_parent()
316 		f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);  in clk_dyn_rcg_set_parent()
320 		f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;  in clk_dyn_rcg_set_parent()
322 	f.src = qcom_find_src_index(hw, rcg->s[bank].parent_map, index);  in clk_dyn_rcg_set_parent()
323 	return configure_bank(rcg, &f);  in clk_dyn_rcg_set_parent()
352 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_recalc_rate()  local
354 	struct mn *mn = &rcg->mn;  in clk_rcg_recalc_rate()
356 	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_recalc_rate()
357 	pre_div = ns_to_pre_div(&rcg->p, ns);  in clk_rcg_recalc_rate()
359 	if (rcg->mn.width) {  in clk_rcg_recalc_rate()
360 		regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);  in clk_rcg_recalc_rate()
364 		if (rcg->clkr.enable_reg != rcg->ns_reg)  in clk_rcg_recalc_rate()
365 			regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &mode);  in clk_rcg_recalc_rate()
377 	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);  in clk_dyn_rcg_recalc_rate()  local
381 	bool banked_p = !!rcg->p[1].pre_div_width;  in clk_dyn_rcg_recalc_rate()
382 	bool banked_mn = !!rcg->mn[1].width;  in clk_dyn_rcg_recalc_rate()
384 	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in clk_dyn_rcg_recalc_rate()
385 	bank = reg_to_bank(rcg, reg);  in clk_dyn_rcg_recalc_rate()
387 	regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);  in clk_dyn_rcg_recalc_rate()
391 		mn = &rcg->mn[bank];  in clk_dyn_rcg_recalc_rate()
392 		regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);  in clk_dyn_rcg_recalc_rate()
396 		if (rcg->ns_reg[0] != rcg->ns_reg[1])  in clk_dyn_rcg_recalc_rate()
402 		pre_div = ns_to_pre_div(&rcg->p[bank], ns);  in clk_dyn_rcg_recalc_rate()
448 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_determine_rate()  local
450 	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, min_rate,  in clk_rcg_determine_rate()
451 			max_rate, p_rate, p, rcg->s.parent_map);  in clk_rcg_determine_rate()
458 	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);  in clk_dyn_rcg_determine_rate()  local
463 	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in clk_dyn_rcg_determine_rate()
464 	bank = reg_to_bank(rcg, reg);  in clk_dyn_rcg_determine_rate()
465 	s = &rcg->s[bank];  in clk_dyn_rcg_determine_rate()
467 	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, min_rate,  in clk_dyn_rcg_determine_rate()
475 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_bypass_determine_rate()  local
476 	const struct freq_tbl *f = rcg->freq_tbl;  in clk_rcg_bypass_determine_rate()
478 	int index = qcom_find_src_index(hw, rcg->s.parent_map, f->src);  in clk_rcg_bypass_determine_rate()
487 static int __clk_rcg_set_rate(struct clk_rcg *rcg, const struct freq_tbl *f)  in __clk_rcg_set_rate()  argument
490 	struct mn *mn = &rcg->mn;  in __clk_rcg_set_rate()
494 	if (rcg->mn.reset_in_cc)  in __clk_rcg_set_rate()
495 		reset_reg = rcg->clkr.enable_reg;  in __clk_rcg_set_rate()
497 		reset_reg = rcg->ns_reg;  in __clk_rcg_set_rate()
499 	if (rcg->mn.width) {  in __clk_rcg_set_rate()
501 		regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, mask);  in __clk_rcg_set_rate()
503 		regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);  in __clk_rcg_set_rate()
505 		regmap_write(rcg->clkr.regmap, rcg->md_reg, md);  in __clk_rcg_set_rate()
507 		regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in __clk_rcg_set_rate()
509 		if (rcg->clkr.enable_reg != rcg->ns_reg) {  in __clk_rcg_set_rate()
510 			regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);  in __clk_rcg_set_rate()
512 			regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);  in __clk_rcg_set_rate()
518 		regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in __clk_rcg_set_rate()
521 	ns = pre_div_to_ns(&rcg->p, f->pre_div - 1, ns);  in __clk_rcg_set_rate()
522 	regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);  in __clk_rcg_set_rate()
524 	regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, 0);  in __clk_rcg_set_rate()
532 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_set_rate()  local
535 	f = qcom_find_freq(rcg->freq_tbl, rate);  in clk_rcg_set_rate()
539 	return __clk_rcg_set_rate(rcg, f);  in clk_rcg_set_rate()
545 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_bypass_set_rate()  local
547 	return __clk_rcg_set_rate(rcg, rcg->freq_tbl);  in clk_rcg_bypass_set_rate()
564 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_lcc_set_rate()  local
569 	f = qcom_find_freq(rcg->freq_tbl, rate);  in clk_rcg_lcc_set_rate()
574 	regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);  in clk_rcg_lcc_set_rate()
575 	ret = __clk_rcg_set_rate(rcg, f);  in clk_rcg_lcc_set_rate()
578 		regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);  in clk_rcg_lcc_set_rate()
585 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_lcc_enable()  local
589 	return regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);  in clk_rcg_lcc_enable()
594 	struct clk_rcg *rcg = to_clk_rcg(hw);  in clk_rcg_lcc_disable()  local
598 	regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);  in clk_rcg_lcc_disable()
603 	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);  in __clk_dyn_rcg_set_rate()  local
606 	f = qcom_find_freq(rcg->freq_tbl, rate);  in __clk_dyn_rcg_set_rate()
610 	return configure_bank(rcg, f);  in __clk_dyn_rcg_set_rate()