96 	u32 l, m, n, config;  in clk_pll_recalc_rate()  local
116 		regmap_read(pll->clkr.regmap, pll->config_reg, &config);  in clk_pll_recalc_rate()
117 		config >>= pll->post_div_shift;  in clk_pll_recalc_rate()
118 		config &= BIT(pll->post_div_width) - 1;  in clk_pll_recalc_rate()
119 		rate /= config + 1;  in clk_pll_recalc_rate()
252 	const struct pll_config *config)  in clk_pll_configure()  argument
257 	regmap_write(regmap, pll->l_reg, config->l);  in clk_pll_configure()
258 	regmap_write(regmap, pll->m_reg, config->m);  in clk_pll_configure()
259 	regmap_write(regmap, pll->n_reg, config->n);  in clk_pll_configure()
261 	val = config->vco_val;  in clk_pll_configure()
262 	val |= config->pre_div_val;  in clk_pll_configure()
263 	val |= config->post_div_val;  in clk_pll_configure()
264 	val |= config->mn_ena_mask;  in clk_pll_configure()
265 	val |= config->main_output_mask;  in clk_pll_configure()
266 	val |= config->aux_output_mask;  in clk_pll_configure()
268 	mask = config->vco_mask;  in clk_pll_configure()
269 	mask |= config->pre_div_mask;  in clk_pll_configure()
270 	mask |= config->post_div_mask;  in clk_pll_configure()
271 	mask |= config->mn_ena_mask;  in clk_pll_configure()
272 	mask |= config->main_output_mask;  in clk_pll_configure()
273 	mask |= config->aux_output_mask;  in clk_pll_configure()
279 		const struct pll_config *config, bool fsm_mode)  in clk_pll_configure_sr()  argument
281 	clk_pll_configure(pll, regmap, config);  in clk_pll_configure_sr()
288 		const struct pll_config *config, bool fsm_mode)  in clk_pll_configure_sr_hpm_lp()  argument
290 	clk_pll_configure(pll, regmap, config);  in clk_pll_configure_sr_hpm_lp()