Lines Matching refs:pll_readl
60 static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg) in pll_readl() function
117 val = pll_readl(pll, PLL_CTRL3); in pll_gf40lp_frac_enable()
122 val = pll_readl(pll, PLL_CTRL4); in pll_gf40lp_frac_enable()
134 val = pll_readl(pll, PLL_CTRL3); in pll_gf40lp_frac_disable()
143 return !(pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_PD); in pll_gf40lp_frac_is_enabled()
162 val = pll_readl(pll, PLL_CTRL1); in pll_gf40lp_frac_set_rate()
169 val = pll_readl(pll, PLL_CTRL2); in pll_gf40lp_frac_set_rate()
180 while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK)) in pll_gf40lp_frac_set_rate()
196 val = pll_readl(pll, PLL_CTRL1); in pll_gf40lp_frac_recalc_rate()
200 val = pll_readl(pll, PLL_CTRL2); in pll_gf40lp_frac_recalc_rate()
234 val = pll_readl(pll, PLL_CTRL1); in pll_gf40lp_laint_enable()
239 val = pll_readl(pll, PLL_CTRL2); in pll_gf40lp_laint_enable()
251 val = pll_readl(pll, PLL_CTRL1); in pll_gf40lp_laint_disable()
260 return !(pll_readl(pll, PLL_CTRL1) & PLL_INT_CTRL1_PD); in pll_gf40lp_laint_is_enabled()
279 val = pll_readl(pll, PLL_CTRL1); in pll_gf40lp_laint_set_rate()
290 while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK)) in pll_gf40lp_laint_set_rate()
306 val = pll_readl(pll, PLL_CTRL1); in pll_gf40lp_laint_recalc_rate()