Lines Matching refs:ARRAY_SIZE
96 ARRAY_SIZE(fixed_rate_clks)); in pxa910_pll_init()
99 ARRAY_SIZE(fixed_factor_clks)); in pxa910_pll_init()
105 ARRAY_SIZE(uart_factor_tbl), NULL); in pxa910_pll_init()
121 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
122 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
123 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
124 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
128 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART…
158 ARRAY_SIZE(apbc_mux_clks)); in pxa910_apb_periph_clk_init()
161 ARRAY_SIZE(apbcp_mux_clks)); in pxa910_apb_periph_clk_init()
164 ARRAY_SIZE(apbc_gate_clks)); in pxa910_apb_periph_clk_init()
167 ARRAY_SIZE(apbcp_gate_clks)); in pxa910_apb_periph_clk_init()
184 …{0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6,…
185 …{0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6,…
186 …{0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0…
187 …{0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0…
188 …{0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT…
213 ARRAY_SIZE(apmu_mux_clks)); in pxa910_axi_periph_clk_init()
216 ARRAY_SIZE(apmu_div_clks)); in pxa910_axi_periph_clk_init()
219 ARRAY_SIZE(apmu_gate_clks)); in pxa910_axi_periph_clk_init()
228 nr_resets_apbc = ARRAY_SIZE(apbc_gate_clks); in pxa910_clk_reset_init()
229 nr_resets_apbcp = ARRAY_SIZE(apbcp_gate_clks); in pxa910_clk_reset_init()