Lines Matching refs:ARRAY_SIZE
97 ARRAY_SIZE(fixed_rate_clks)); in pxa168_pll_init()
100 ARRAY_SIZE(fixed_factor_clks)); in pxa168_pll_init()
106 ARRAY_SIZE(uart_factor_tbl), NULL); in pxa168_pll_init()
125 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
126 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
127 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2…
128 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
129 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
130 …{0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4,…
131 …{0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4,…
132 …{0, "ssp4_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP4, 4,…
161 ARRAY_SIZE(apbc_mux_clks)); in pxa168_apb_periph_clk_init()
164 ARRAY_SIZE(apbc_gate_clks)); in pxa168_apb_periph_clk_init()
182 …{0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6,…
183 …{0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6,…
184 …{0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0…
185 …{0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0…
186 …{0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT…
211 ARRAY_SIZE(apmu_mux_clks)); in pxa168_axi_periph_clk_init()
214 ARRAY_SIZE(apmu_div_clks)); in pxa168_axi_periph_clk_init()
217 ARRAY_SIZE(apmu_gate_clks)); in pxa168_axi_periph_clk_init()
226 nr_resets = ARRAY_SIZE(apbc_gate_clks); in pxa168_clk_reset_init()