83 	void __iomem *apmu_base;  in mmp2_clk_init()  local
92 	apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);  in mmp2_clk_init()
93 	if (apmu_base == NULL) {  in mmp2_clk_init()
337 				apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);  in mmp2_clk_init()
341 				CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,  in mmp2_clk_init()
345 	clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,  in mmp2_clk_init()
349 	clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,  in mmp2_clk_init()
353 	clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,  in mmp2_clk_init()
357 	clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,  in mmp2_clk_init()
361 	clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,  in mmp2_clk_init()
368 				apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
372 				CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,  in mmp2_clk_init()
377 				apmu_base + APMU_DISP0, 0x1b, &clk_lock);  in mmp2_clk_init()
381 				apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);  in mmp2_clk_init()
385 				apmu_base + APMU_DISP0, 0x1024, &clk_lock);  in mmp2_clk_init()
391 				apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
395 				CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,  in mmp2_clk_init()
400 				apmu_base + APMU_DISP1, 0x1b, &clk_lock);  in mmp2_clk_init()
404 				apmu_base + APMU_CCIC0, 0x1800, &clk_lock);  in mmp2_clk_init()
410 				apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
414 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,  in mmp2_clk_init()
419 				apmu_base + APMU_CCIC0, 0x1b, &clk_lock);  in mmp2_clk_init()
423 				apmu_base + APMU_CCIC0, 0x24, &clk_lock);  in mmp2_clk_init()
427 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,  in mmp2_clk_init()
432 				apmu_base + APMU_CCIC0, 0x300, &clk_lock);  in mmp2_clk_init()
438 				apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
442 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,  in mmp2_clk_init()
447 				apmu_base + APMU_CCIC1, 0x1b, &clk_lock);  in mmp2_clk_init()
451 				apmu_base + APMU_CCIC1, 0x24, &clk_lock);  in mmp2_clk_init()
455 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,  in mmp2_clk_init()
460 				apmu_base + APMU_CCIC1, 0x300, &clk_lock);  in mmp2_clk_init()