222 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_enable()  local
226 	if (pclk->lock)  in xgene_clk_enable()
227 		spin_lock_irqsave(pclk->lock, flags);  in xgene_clk_enable()
229 	if (pclk->param.csr_reg != NULL) {  in xgene_clk_enable()
230 		pr_debug("%s clock enabled\n", pclk->name);  in xgene_clk_enable()
232 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_enable()
233 					pclk->param.reg_clk_offset);  in xgene_clk_enable()
234 		data |= pclk->param.reg_clk_mask;  in xgene_clk_enable()
235 		xgene_clk_write(data, pclk->param.csr_reg +  in xgene_clk_enable()
236 					pclk->param.reg_clk_offset);  in xgene_clk_enable()
238 			pclk->name, __pa(pclk->param.csr_reg),  in xgene_clk_enable()
239 			pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,  in xgene_clk_enable()
243 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_enable()
244 					pclk->param.reg_csr_offset);  in xgene_clk_enable()
245 		data &= ~pclk->param.reg_csr_mask;  in xgene_clk_enable()
246 		xgene_clk_write(data, pclk->param.csr_reg +  in xgene_clk_enable()
247 					pclk->param.reg_csr_offset);  in xgene_clk_enable()
249 			pclk->name, __pa(pclk->param.csr_reg),  in xgene_clk_enable()
250 			pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,  in xgene_clk_enable()
254 	if (pclk->lock)  in xgene_clk_enable()
255 		spin_unlock_irqrestore(pclk->lock, flags);  in xgene_clk_enable()
262 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_disable()  local
266 	if (pclk->lock)  in xgene_clk_disable()
267 		spin_lock_irqsave(pclk->lock, flags);  in xgene_clk_disable()
269 	if (pclk->param.csr_reg != NULL) {  in xgene_clk_disable()
270 		pr_debug("%s clock disabled\n", pclk->name);  in xgene_clk_disable()
272 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_disable()
273 					pclk->param.reg_csr_offset);  in xgene_clk_disable()
274 		data |= pclk->param.reg_csr_mask;  in xgene_clk_disable()
275 		xgene_clk_write(data, pclk->param.csr_reg +  in xgene_clk_disable()
276 					pclk->param.reg_csr_offset);  in xgene_clk_disable()
279 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_disable()
280 					pclk->param.reg_clk_offset);  in xgene_clk_disable()
281 		data &= ~pclk->param.reg_clk_mask;  in xgene_clk_disable()
282 		xgene_clk_write(data, pclk->param.csr_reg +  in xgene_clk_disable()
283 					pclk->param.reg_clk_offset);  in xgene_clk_disable()
286 	if (pclk->lock)  in xgene_clk_disable()
287 		spin_unlock_irqrestore(pclk->lock, flags);  in xgene_clk_disable()
292 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_is_enabled()  local
295 	if (pclk->param.csr_reg != NULL) {  in xgene_clk_is_enabled()
296 		pr_debug("%s clock checking\n", pclk->name);  in xgene_clk_is_enabled()
297 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_is_enabled()
298 					pclk->param.reg_clk_offset);  in xgene_clk_is_enabled()
299 		pr_debug("%s clock is %s\n", pclk->name,  in xgene_clk_is_enabled()
300 			data & pclk->param.reg_clk_mask ? "enabled" :  in xgene_clk_is_enabled()
304 	if (pclk->param.csr_reg == NULL)  in xgene_clk_is_enabled()
306 	return data & pclk->param.reg_clk_mask ? 1 : 0;  in xgene_clk_is_enabled()
312 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_recalc_rate()  local
315 	if (pclk->param.divider_reg) {  in xgene_clk_recalc_rate()
316 		data = xgene_clk_read(pclk->param.divider_reg +  in xgene_clk_recalc_rate()
317 					pclk->param.reg_divider_offset);  in xgene_clk_recalc_rate()
318 		data >>= pclk->param.reg_divider_shift;  in xgene_clk_recalc_rate()
319 		data &= (1 << pclk->param.reg_divider_width) - 1;  in xgene_clk_recalc_rate()
322 			pclk->name, parent_rate / data, parent_rate);  in xgene_clk_recalc_rate()
326 			pclk->name, parent_rate, parent_rate);  in xgene_clk_recalc_rate()
334 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_set_rate()  local
340 	if (pclk->lock)  in xgene_clk_set_rate()
341 		spin_lock_irqsave(pclk->lock, flags);  in xgene_clk_set_rate()
343 	if (pclk->param.divider_reg) {  in xgene_clk_set_rate()
348 		divider &= (1 << pclk->param.reg_divider_width) - 1;  in xgene_clk_set_rate()
349 		divider <<= pclk->param.reg_divider_shift;  in xgene_clk_set_rate()
352 		data = xgene_clk_read(pclk->param.divider_reg +  in xgene_clk_set_rate()
353 				pclk->param.reg_divider_offset);  in xgene_clk_set_rate()
354 		data &= ~((1 << pclk->param.reg_divider_width) - 1);  in xgene_clk_set_rate()
356 		xgene_clk_write(data, pclk->param.divider_reg +  in xgene_clk_set_rate()
357 					pclk->param.reg_divider_offset);  in xgene_clk_set_rate()
358 		pr_debug("%s clock set rate %ld\n", pclk->name,  in xgene_clk_set_rate()
364 	if (pclk->lock)  in xgene_clk_set_rate()
365 		spin_unlock_irqrestore(pclk->lock, flags);  in xgene_clk_set_rate()
373 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_round_rate()  local
377 	if (pclk->param.divider_reg) {  in xgene_clk_round_rate()