400 		struct xgene_dev_parameters *parameters, spinlock_t *lock)  in xgene_register_clk()  argument
423 	apmclk->param = *parameters;  in xgene_register_clk()
448 	struct xgene_dev_parameters parameters;  in xgene_devclk_init()  local
456 	parameters.csr_reg = NULL;  in xgene_devclk_init()
457 	parameters.divider_reg = NULL;  in xgene_devclk_init()
476 			parameters.divider_reg = map_res;  in xgene_devclk_init()
478 			parameters.csr_reg = map_res;  in xgene_devclk_init()
480 	if (of_property_read_u32(np, "csr-offset", &parameters.reg_csr_offset))  in xgene_devclk_init()
481 		parameters.reg_csr_offset = 0;  in xgene_devclk_init()
482 	if (of_property_read_u32(np, "csr-mask", &parameters.reg_csr_mask))  in xgene_devclk_init()
483 		parameters.reg_csr_mask = 0xF;  in xgene_devclk_init()
485 				&parameters.reg_clk_offset))  in xgene_devclk_init()
486 		parameters.reg_clk_offset = 0x8;  in xgene_devclk_init()
487 	if (of_property_read_u32(np, "enable-mask", &parameters.reg_clk_mask))  in xgene_devclk_init()
488 		parameters.reg_clk_mask = 0xF;  in xgene_devclk_init()
490 				&parameters.reg_divider_offset))  in xgene_devclk_init()
491 		parameters.reg_divider_offset = 0;  in xgene_devclk_init()
493 				&parameters.reg_divider_width))  in xgene_devclk_init()
494 		parameters.reg_divider_width = 0;  in xgene_devclk_init()
496 				&parameters.reg_divider_shift))  in xgene_devclk_init()
497 		parameters.reg_divider_shift = 0;  in xgene_devclk_init()
501 		of_clk_get_parent_name(np, 0), &parameters, &clk_lock);  in xgene_devclk_init()
513 	if (parameters.csr_reg)  in xgene_devclk_init()
514 		iounmap(parameters.csr_reg);  in xgene_devclk_init()
515 	if (parameters.divider_reg)  in xgene_devclk_init()
516 		iounmap(parameters.divider_reg);  in xgene_devclk_init()