67 static void __init core_mux_init(struct device_node *np)  in core_mux_init()  argument
79 	rc = of_property_read_u32(np, "reg", &offset);  in core_mux_init()
81 		pr_err("%s: could not get reg property\n", np->name);  in core_mux_init()
86 	count = of_property_count_strings(np, "clock-names");  in core_mux_init()
88 		pr_err("%s: get clock count error\n", np->name);  in core_mux_init()
96 		parent_names[i] = of_clk_get_parent_name(np, i);  in core_mux_init()
102 	cmux_clk->reg = of_iomap(np, 0);  in core_mux_init()
108 	rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", 0,  in core_mux_init()
115 	cmux_clk->clk_per_pll = of_property_count_strings(clkspec.np,  in core_mux_init()
117 	of_node_put(clkspec.np);  in core_mux_init()
123 	rc = of_property_read_string_index(np, "clock-output-names",  in core_mux_init()
126 		pr_err("%s: read clock names error\n", np->name);  in core_mux_init()
143 	rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);  in core_mux_init()
146 		       np->name);  in core_mux_init()
158 static void __init core_pll_init(struct device_node *np)  in core_pll_init()  argument
167 	base = of_iomap(np, 0);  in core_pll_init()
178 		pr_debug("PLL:%s is disabled\n", np->name);  in core_pll_init()
183 	parent_name = of_clk_get_parent_name(np, 0);  in core_pll_init()
185 		pr_err("PLL: %s must have a parent\n", np->name);  in core_pll_init()
189 	count = of_property_count_strings(np, "clock-output-names");  in core_pll_init()
191 		pr_err("%s: clock is not supported\n", np->name);  in core_pll_init()
204 		rc = of_property_read_string_index(np, "clock-output-names",  in core_pll_init()
207 			pr_err("%s: could not get clock names\n", np->name);  in core_pll_init()
234 	rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);  in core_pll_init()
237 		       np->name);  in core_pll_init()
255 	struct device_node *np = of_get_parent(node);  in sysclk_init()  local
258 	if (!np) {  in sysclk_init()
263 	if (of_property_read_u32(np, "clock-frequency", &rate)) {  in sysclk_init()
268 	of_property_read_string(np, "clock-output-names", &clk_name);  in sysclk_init()
272 		of_clk_add_provider(np, of_clk_src_simple_get, clk);  in sysclk_init()
275 static void __init pltfrm_pll_init(struct device_node *np)  in pltfrm_pll_init()  argument
283 	base = of_iomap(np, 0);  in pltfrm_pll_init()
285 		pr_err("%s(): %s: of_iomap() failed\n", __func__, np->name);  in pltfrm_pll_init()
296 		pr_debug("%s(): %s: Disabled\n", __func__, np->name);  in pltfrm_pll_init()
301 	parent_name = of_clk_get_parent_name(np, 0);  in pltfrm_pll_init()
304 		       __func__, np->name);  in pltfrm_pll_init()
308 	i = of_property_count_strings(np, "clock-output-names");  in pltfrm_pll_init()
311 		       __func__, np->name, i);  in pltfrm_pll_init()
322 		_errno = of_property_read_string_index(np, "clock-output-names",  in pltfrm_pll_init()
326 			       __func__, np->name, _errno);  in pltfrm_pll_init()
334 			       __func__, np->name,  in pltfrm_pll_init()
340 	_errno = of_clk_add_provider(np, of_clk_src_onecell_get, cod);  in pltfrm_pll_init()
343 		       __func__, np->name, _errno);  in pltfrm_pll_init()