191 of_at91_clk_master_get_characteristics(struct device_node *np)  in of_at91_clk_master_get_characteristics()  argument
199 	if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output))  in of_at91_clk_master_get_characteristics()
202 	of_property_read_u32_array(np, "atmel,clk-divisors",  in of_at91_clk_master_get_characteristics()
206 		of_property_read_bool(np, "atmel,master-clk-have-div3-pres");  in of_at91_clk_master_get_characteristics()
216 of_at91_clk_master_setup(struct device_node *np, struct at91_pmc *pmc,  in of_at91_clk_master_setup()  argument
224 	const char *name = np->name;  in of_at91_clk_master_setup()
227 	num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");  in of_at91_clk_master_setup()
232 		parent_names[i] = of_clk_get_parent_name(np, i);  in of_at91_clk_master_setup()
237 	of_property_read_string(np, "clock-output-names", &name);  in of_at91_clk_master_setup()
239 	characteristics = of_at91_clk_master_get_characteristics(np);  in of_at91_clk_master_setup()
243 	irq = irq_of_parse_and_map(np, 0);  in of_at91_clk_master_setup()
253 	of_clk_add_provider(np, of_clk_src_simple_get, clk);  in of_at91_clk_master_setup()
260 void __init of_at91rm9200_clk_master_setup(struct device_node *np,  in of_at91rm9200_clk_master_setup()  argument
263 	of_at91_clk_master_setup(np, pmc, &at91rm9200_master_layout);  in of_at91rm9200_clk_master_setup()
266 void __init of_at91sam9x5_clk_master_setup(struct device_node *np,  in of_at91sam9x5_clk_master_setup()  argument
269 	of_at91_clk_master_setup(np, pmc, &at91sam9x5_master_layout);  in of_at91sam9x5_clk_master_setup()