Lines Matching refs:CHB
240 #define CHB 0x40 /* channel B offset */ macro
343 write_reg16(info, CHB + IMR, info->imrb_value); in irq_disable()
353 write_reg16(info, CHB + IMR, info->imrb_value); in irq_enable()
1051 irq_disable(info, CHB, IRQ_CTS); in cts_change()
1086 irq_disable(info, CHB, IRQ_DCD); in dcd_change()
1186 isr = read_reg16(info, CHB + ISR); in mgslpc_isr()
1389 irq_enable(info, CHB, IRQ_DCD | IRQ_CTS); in mgslpc_program_hw()
2961 write_reg(info, CHB + MODE, val); in enable_auxclk()
2973 write_reg(info, CHB + CCR0, 0xc0); in enable_auxclk()
2986 write_reg(info, CHB + CCR1, 0x17); in enable_auxclk()
3001 write_reg(info, CHB + CCR2, 0x38); in enable_auxclk()
3003 write_reg(info, CHB + CCR2, 0x30); in enable_auxclk()
3016 write_reg(info, CHB + CCR4, 0x50); in enable_auxclk()
3022 mgslpc_set_rate(info, CHB, info->params.clock_speed); in enable_auxclk()
3024 mgslpc_set_rate(info, CHB, 921600); in enable_auxclk()
3057 irq_disable(info, CHB, 0xffff); in hdlc_mode()
3258 irq_enable(info, CHB, IRQ_CTS); in hdlc_mode()
3375 write_reg(info, CHB + CCR0, 0x80); in reset_device()
3377 write_reg(info, CHB + MODE, 0); in reset_device()
3381 irq_disable(info, CHB, 0xffff); in reset_device()
3427 irq_disable(info, CHB, 0xffff); in async_mode()
3577 irq_enable(info, CHB, IRQ_CTS); in async_mode()
3610 if (read_reg(info, CHB + VSTR) & BIT7) in get_signals()
3612 if (read_reg(info, CHB + STAR) & BIT1) in get_signals()